PMOS Cascode Feedthrough Switch for Low Leakage Blocking
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Solution Overview
Problem
Existing switch circuits struggle to maintain low leakage current when off and prevent transistor voltage ratings from being exceeded during normal operation, especially in AC voltage environments and scenarios where control over signal or supply voltage is limited.
Innovation Solution
A feedthrough switch using a cascode circuit with two PMOS devices in series, coupled with a PMOS blocking voltage follower circuit and an overstress prevention voltage supply, to dynamically bias the transistors and maintain them in a non-conductive state while preventing voltage overstress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a switch is formed of transistors to enable selective bypass operation, then the switch can be controlled to turn bypass on and off, but leakage current passes across the switch when open
Solution Approach 1:
The switch is divided into multiple transistor stages (first transistor and second transistor in series) rather than using a single transistor. This segmentation allows each transistor to share the voltage blocking duty, enabling better leakage current suppression while maintaining controllability for selective bypass operation.
Solution Approach 2:
A voltage follower circuit is introduced as an intermediary component to dynamically generate gate voltages for the transistors. This intermediary circuit tracks the input voltage signal and provides appropriate biasing to keep transistors in the desired state (off for blocking, on for bypass), thereby reducing leakage current while maintaining operational control.
2Adaptability or versatility
If transistors are used in AC voltage circuits to enable switching operation, then the switch can handle AC signals, but the rated voltage of transistors may be exceeded during AC waveform cycles
Solution Approach 1:
The voltage blocking function is segmented across multiple transistor stages. By placing transistors in series and using a voltage follower to dynamically bias their gates, the circuit distributes the voltage stress across multiple devices rather than placing the full AC voltage swing across a single transistor, preventing rated voltage exceedance while maintaining AC signal handling capability.
Solution Approach 2:
The voltage follower circuit dynamically adjusts the gate voltages of the transistors in real-time to track the input AC voltage signal. This dynamic biasing ensures that transistors remain in the appropriate operating region throughout the AC waveform cycles, preventing voltage overstress while enabling full AC voltage handling.
3Adaptability or versatility
If control over signal voltage and supply voltage is limited (as in USB retimer scenarios), then the switch can operate in externally voltage-controlled environments, but it becomes difficult to maintain low leakage current and prevent voltage overstress
Solution Approach 1:
The voltage follower circuit implements feedback by continuously monitoring the input voltage signal and using this information to dynamically generate appropriate gate bias voltages for the transistors. This feedback mechanism allows the circuit to adapt to externally controlled voltage conditions (such as USB retimer environments) while automatically maintaining transistors in safe operating regions with minimal leakage current.
Solution Approach 2:
The circuit uses the externally provided voltage signal itself to generate the necessary control voltages for the transistors through the voltage follower. Rather than requiring separate control voltage supplies, the circuit serves itself by deriving its own biasing needs from the input signal, enabling operation in externally voltage-controlled environments while maintaining reliability.
Data Source
AI summary
A feedthrough switch that prevents, in a blocking mode, voltage signals from being transmitted via a feedthrough path, comprising a cascode circuit comprising two PMOS devices coupled in series. One of the PMOS devices is coupled to receive an input voltage signal at its source and the other coupled to a center node. A gate of each PMOS is biased using a biasing circuit including a voltage follower that provides a biasing voltage that tracks the input voltage signal up to a supply voltage of the voltage follower. The biasing voltage keeps both PMOS devices in a non-conductive state while the voltage signal is below the supply voltage. An overstress prevention voltage supply is coupled to the center node and maintains the center node at a fixed voltage to ensure that both PMOS devices remain within their respective rated voltages across the full range of the voltage signal.