PMOS Transistor Cell Layout With Biased Insulating Gates
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Solution Overview
Problem
In CMOS technology, PMOS transistors have lower performance compared to NMOS transistors, and increasing their size or doping concentrations to compensate is not efficient, while insulating trenches can release strain in PMOS transistors, and alternative insulation methods like non-active gates introduce additional drawbacks.
Innovation Solution
The design includes PMOS transistors with strained channel regions and uses insulating gates that are biased to the power supply rail, with insulating gate contacts positioned above and straddling both the active area and insulating region to maintain strain and reduce the complexity of connection circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If insulating gates are used to isolate adjacent cells, then cell insulation is achieved without releasing strain, but additional connection complexity is introduced
Solution Approach 1:
The patent merges the function of insulating gates with the power supply network by connecting the insulating gates to the power supply rail. This combination eliminates the need for separate connection structures, reducing overall device complexity while maintaining the isolation function.
Solution Approach 2:
The insulating gates serve multiple functions: they provide lateral isolation between adjacent PMOS transistors, maintain strain in the channel regions, and act as power supply connections. This multi-functionality reduces the need for additional dedicated structures, simplifying the overall device design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance of PMOS transistors by maintaining strain and allowing for increased active area width without adding complexity to the manufacturing process, improving transistor cell performance.
Implementation Method 1
A transistor with a strained channel region, or strained transistor, is a field-effect transistor where a channel-forming semiconductor region is mechanically strained. The presence of strain in the channel-forming region enables to increase the rapidity of the transistor, by particularly increasing the mobility of holes for a PMOS-type transistor.
Implementation Method 2
a first insulating gate contact coupled to the first insulating gate and forming a fourth insulation with the first active area, the first insulating gate contact being configured to couple the first insulating gate to a power supply rail
Data Source
AI summary
An electronic device including a first active area of a first transistor, a first insulating region forming a first insulation of the first active area, a first insulating gate extending above the first active area and forming a second insulation of the first active area, and a first insulating gate contact coupled to the first insulating gate and positioned above both the first active area and the first insulating region, wherein the first insulating gate contact couples the first insulating gate to a power supply rail.