PMOS Source-Drain Stack for Low-Resistance CoSi2 Contacts

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Solution Overview

Problem

The challenge in fabricating PMOS transistors with small line widths is the insufficient Si content in the SiGe epitaxial structure, which hinders the formation of the low resistance phase CoSi2, leading to increased resistance at the source-drain and potential agglomeration issues at high temperatures.

Innovation Solution

A method involving the growth of a SiGe layer within source-drain trenches, followed by the deposition of a Si thin film layer and a Co thin film layer, with an annealing treatment to form a low resistance CoSi2 phase. This process ensures sufficient Si for reaction with Co, optimizing the PMOS transistor performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If SiGe epitaxial structure is used in PMOS source-drain, then carrier mobility is improved, but Si content becomes insufficient for forming low resistance CoSi2 phase

Engineering Contradiction:

Improvecarrier mobilityVSAvoidSi content

Core Design Contradiction:

SpeedVSQuantity of substance

Solution Approach 1:

The source-drain structure is segmented into multiple layers: SiGe layer for mobility enhancement, intermediate Si layer for providing sufficient Si content, and CoSi2 layer for low resistance. This segmentation allows each layer to fulfill its specific function without compromising the others.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

An intermediate Si layer is introduced between the SiGe layer and the Co layer. This intermediate layer acts as a mediator that provides sufficient Si content for CoSi2 formation while allowing the SiGe layer to maintain its mobility-enhancing properties.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If temperature is increased to form low resistance CoSi2 phase, then resistance at source-drain is reduced, but CoSi2 agglomeration occurs causing line breakage

Engineering Contradiction:

Improveresistance at source-drainVSAvoidCoSi2 agglomeration

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The intermediate Si layer is prepared in advance with sufficient thickness before Co deposition. This preliminary action ensures that during the annealing process, there is enough Si available to form a continuous CoSi2 layer without agglomeration, even at the required formation temperature.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The thickness of the intermediate Si layer is precisely controlled to optimize the balance between providing sufficient Si for CoSi2 formation and preventing excessive Si that would require higher temperatures. This parameter control allows CoSi2 formation at moderate temperatures without agglomeration.

Inventive Principle:

Principle #35Parameter changes

3Reliability

If NiSi is used for source-drain, then low resistance is achieved, but phase transition to high resistance NiSi2 occurs at temperatures above 650°C

Engineering Contradiction:

ImproveresistanceVSAvoidprocess temperature compatibility

Core Design Contradiction:

ReliabilityVSTemperature

Solution Approach 1:

Instead of using NiSi which has limited temperature tolerance, the patent uses CoSi2 formation process with an intermediate Si layer that is consumed during the reaction. This approach sacrifices the intermediate Si layer but achieves temperature-compatible low resistance contact suitable for subsequent high-temperature processes.

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed method ensures the formation of a low resistance CoSi2 phase without increasing the resistance at the source-drain, thereby improving the performance and reliability of PMOS transistors with small line widths.

Implementation Method 1

after a Rapid Thermal Processing (RTP) (250° C. ̃410° C.), the Co film diffuses into Si as a diffusion source, to form Co2Si first, and as the temperature of RTP (410° C. ̃510° C.) increases, the Co film further diffuses and forms CoSi gradually

Methodology Applied

Scientific EffectDiffusion: Diffusion

Implementation Method 2

after a Rapid Thermal Processing (RTP) (250° C. ̃410° C.), the Co film diffuses into Si

Methodology Applied

Scientific EffectRapid Thermal Processing: Heating

Data Source

PatentUS20250194187A1PMOS transistor and method of preparing PMOS transistor, CMOS circuit and method of preparing CMOS circuit

Publication Date: 2025.06.12 SWAYSURE TECHNOLOGY CO LTD

AI summary

A method of preparing a PMOS transistor includes: providing a substrate, and forming source-drain trenches on the substrate; growing SiGe material within the source-drain trenches to form a SiGe layer, and growing a Si thin film layer on a surface of the SiGe layer to form a stacked layer structure of the SiGe layer and the Si thin film layer, and growing a first Co thin film layer on the stacked layer structure, and performing an annealing treatment, to make Co in the first Co thin film layer react with Si in the Si thin film layer to form a first CoSi2 thin film layer; an overall structure formed within the source-drain trenches is a source-drain, and the first CoSi2 thin film layer is an upper structure of the source-drain.