PMOS Coupling Circuit for Low Output Voltage Under Negative Transients
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Solution Overview
Problem
Existing output driver circuits face challenges in achieving a low voltage output level while protecting against negative voltages, as NMOS transistors used for low voltage drop can lead to parasitic diode forward biasing and increased voltage drop due to diode connection for protection.
Innovation Solution
A coupling circuit utilizing p-channel field-effect transistors with a charge pump circuit to generate a negative potential for controlling gate voltages, along with a limitation circuit to prevent overvoltage and a separation circuit to actively turn off transistors during negative voltages, ensuring a low voltage output level and protection against damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If an NMOS transistor is used for low voltage drop, then the voltage output low level is reduced, but the parasitic diode becomes forward biased when negative voltages are present
Solution Approach 1:
A diode is introduced as an intermediary protective element connected between the output terminal and the NMOS transistor. This diode blocks negative voltages from reaching the transistor, preventing parasitic diode forward biasing while allowing the NMOS to maintain its low voltage drop characteristic during normal operation
Solution Approach 2:
The protective diode is pre-configured in the circuit to provide beforehand protection against negative voltage conditions. By being in place before any negative voltage event occurs, it prevents damage to the NMOS transistor and its associated parasitic diodes, ensuring reliable operation
2Reliability
If a diode is connected between the output terminal and the NMOS transistor for protection, then protection against negative voltages is achieved, but the voltage drop across the diode increases the voltage output low level
Solution Approach 1:
The circuit uses a PMOS transistor instead of a diode for voltage level control. By changing the device type from diode to transistor and adjusting the gate voltage parameters (using negative voltages from a charge pump), the circuit achieves both protection and low voltage drop without the inherent 0.7V forward voltage drop of a diode
Solution Approach 2:
Different parts of the circuit have specialized functions: the PMOS transistor handles the low voltage drop path locally at the output, while the charge pump circuit provides the necessary negative gate voltage control locally at the transistor gate, enabling the transistor to operate in a state that provides both protection and low impedance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables a low voltage output level with protection against negative voltages and overvoltages, preventing current flow that could damage the circuit, by effectively managing gate voltages and transistor states.
Implementation Method 1
a gate control circuit with a charge pump circuit which is configured to generate a negative potential
Data Source
AI summary
A coupling circuit has a first and a second transistor (P1, P2) of a p-channel field-effect transistor type. A drain terminal of the first transistor (P1) is connected to a signal input (1), source terminals of the first and the second transistor (P1, P2) are commonly connected to a signal output (2), bulk terminals of the first and the second transistor (P1, P2) are commonly connected to a drain terminal of the second transistor (P2), and a gate terminal of the first transistor (P1) is connected to a gate terminal of the second transistor (P2). The coupling circuit further comprises a gate control circuit (10) with a charge pump circuit (110) which is configured to generate a negative potential. The gate control circuit (10) is configured to control a gate voltage at the gate terminals of the first and the second transistor (P1, P2) based on a negative potential.


