pMOS Decoupling Capacitor Cell for IC Noise Reduction
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Solution Overview
Problem
Cell-based ICs face issues with noise and high power consumption due to high-speed switching, which causes significant pulse-like current flows in power and ground wiring, leading to potential circuit malfunctions and increased leak current, especially when using nMOS transistors as decoupling capacitors.
Innovation Solution
A decoupling capacitor cell comprising a pMOS transistor and a two-layer metal layer capacitor is placed in unused regions of the IC, connected to power and ground wiring, reducing leak current and power consumption by using only pMOS transistors and ensuring sufficient decoupling capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If nMOS transistor is used for decoupling capacitor, then decoupling capacity is achieved, but leak current increases significantly (about 10 times higher than pMOS)
Solution Approach 1:
The patent changes the transistor type parameter from nMOS to pMOS for the decoupling capacitor. This parameter change reduces the leak current by approximately 10 times while maintaining sufficient decoupling capacity, directly resolving the contradiction between achieving decoupling function and minimizing energy loss.
2Productivity
If fining process is used to reduce transistor size, then device integration is improved, but gate oxide film thickness decreases causing insufficient insulation and increased leak current
Solution Approach 1:
The patent changes the transistor type from nMOS to pMOS, which has inherently lower leak current characteristics. This parameter change compensates for the reduced gate oxide film thickness caused by fining process, maintaining sufficient insulation and preventing excessive leak current even as device integration increases.
3Speed
If high-speed switching is implemented, then logic circuit speed is improved, but pulse-like current flow increases causing power and ground potential variation
Solution Approach 1:
The patent introduces a pMOS-based decoupling capacitor as an intermediary element between the power supply and ground. This decoupling capacitor absorbs the pulse-like current flows generated by high-speed switching, preventing direct transmission to the power and ground wirings, thereby reducing potential variation and noise while maintaining high switching speeds.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces ground noise and power consumption while maintaining high switching speeds, with leak current reduced to about 1/10 compared to traditional nMOS-based solutions, and secures sufficient decoupling metal capacity without damaging the gate oxide film.
Implementation Method 1
a first decoupling capacitor formed by only a pMOS transistor
Implementation Method 2
a second decoupling capacitor formed by two metal layers
Data Source
AI summary
A decoupling capacitor cell includes: a first decoupling capacitor formed by only a pMOS transistor; and a second decoupling capacitor formed by two metal layers. The decoupling capacitor cell is arranged in an unused region not occupied by basic cells in a cell-based IC and is connected to a power wiring and a ground wiring.