Elevated Strain Interface for PMOS Channel Performance
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Solution Overview
Problem
Current PMOS transistor devices do not effectively enhance strain in the channel region, limiting device performance and speed due to the lack of a strain-inducing material interface above the substrate surface.
Innovation Solution
The method involves forming a semiconductor substructure with a strain-inducing material interface above the substrate surface by creating a recess under the gate structure, filling it with a strain material like silicon germanium, and ensuring the interface between the strain material and spacer is at least 2 nm above the substrate, thereby introducing compressive strain for improved PMOS performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If epitaxial growth of silicon on silicon-germanium underlayer is used to apply compressive strain, then PMOS device performance is enhanced, but the strain material interface must be positioned at a specific height above substrate surface to achieve optimal strain enhancement
Solution Approach 1:
The patent extends the strain material interface vertically above the substrate surface by forming elevated source/drain regions. This dimensional change from planar to elevated structure allows the strain material-sidewall interface to be positioned at a controlled height (e.g., 2 nm above substrate) to optimize strain enhancement in the channel region while maintaining manufacturing feasibility through selective epitaxial growth
Solution Approach 2:
The patent applies strain material (silicon-germanium) specifically in the source/drain regions adjacent to the channel, creating a localized strain field. The elevated interface position is precisely controlled to provide optimal strain enhancement where needed (in the channel region) without requiring uniform strain throughout the entire device structure
2Speed
If strain inducing material is used in source-drain regions, then device speed is improved, but the interface between strain material and spacer must be positioned above substrate surface to maximize strain effect
Solution Approach 1:
The patent creates an elevated strain material interface above the substrate surface by forming raised source/drain regions through selective epitaxial growth. This vertical dimensionality allows the strain material-sidewall interface to be positioned at an optimized height to maximize strain-induced carrier mobility enhancement, thereby improving device speed without requiring complex external strain application mechanisms
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances PMOS device performance by up to 3% compared to traditional strained PMOS devices, as evidenced by TOAD simulations and current gain measurements, by increasing the strain in the channel region.
Implementation Method 1
The lattice of the silicon layer is stretched to follow the larger lattice constant of the underlying silicon-germanium. This causes compression of the channel.
Data Source
AI summary
A semiconductor substructure with improved performance and a method of forming the same is described. In one embodiment, the semiconductor substructure includes a substrate, having an upper surface; a gate structure formed over the substrate; a spacer formed along a sidewall of the gate structure; and a source/drain structure disposed adjacent the gate structure. The source/drain structures is formed of a strain material and is disposed in an recess that extends below the upper surface of the substrate. An interface between the spacer and the source-drain structure can be at least 2 nm above the upper surface of the substrate.