PMOS Epitaxial Protection Layer for Leakage Current Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The miniaturization of semiconductor devices leads to challenges in precisely defining recess regions during epitaxial growth, resulting in issues like short channel effects and increased leakage current, which affect the quality and efficiency of MOS transistors.
Innovation Solution
A semiconductor device and fabrication method involving the formation of a protection layer made of oxide material on an epitaxial layer, along with a contact etching stop layer, to improve leakage current issues and enhance device reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If selective epitaxial growth is performed to form epitaxial layers for applying stress to increase carrier mobility, then carrier mobility is improved, but manufacturing precision deteriorates due to difficulty in precisely defining recess regions during miniaturization
Solution Approach 1:
The patent applies preliminary action by forming the protection layer on the epitaxial layer before subsequent processing steps. This protection layer is prepared in advance to prevent potential damages that may occur during later fabrication processes, thereby ensuring the integrity of the epitaxial structure while maintaining the stress-induced carrier mobility enhancement.
Solution Approach 2:
The protection layer acts as an intermediary between the epitaxial layer and the external environment or subsequent processing steps. This intermediate layer prevents direct interaction that could cause damage to the light doped drain region, thus maintaining manufacturing precision while preserving the carrier mobility benefits.
2Reliability
If recess regions are defined in the substrate for epitaxial layer formation, then carrier mobility is improved through stress application, but device reliability deteriorates due to damages to the light doped drain region causing short channel effect and increased leakage current
Solution Approach 1:
The protection layer provides beforehand cushioning by being formed on the epitaxial layer prior to subsequent processing steps. This protective barrier prevents potential damages to the light doped drain region during fabrication, thereby preventing short channel effects and reducing leakage current while maintaining the carrier mobility benefits.
Solution Approach 2:
The protection layer serves as an intermediary that protects the epitaxial structure from harmful factors during processing. It acts as a buffer that prevents direct damage to the light doped drain region, thus eliminating the source of leakage current while preserving the stress-induced carrier mobility enhancement.
3Productivity
If the semiconductor device is miniaturized to increase integration density, then productivity is improved, but manufacturing precision deteriorates making it difficult to precisely define recess regions
Solution Approach 1:
The protection layer is formed as a preliminary structure before subsequent miniaturization and processing steps. This preliminary protection ensures that even as devices are miniaturized to increase integration density, the epitaxial structures remain intact and precisely defined, overcoming the manufacturing precision challenges associated with miniaturization.
Solution Approach 2:
The protection layer functions as a thin film structure that can be precisely formed and controlled even at miniaturized dimensions. This thin protective film maintains manufacturing precision during miniaturization by providing a stable reference structure that prevents damage to the underlying epitaxial layers while allowing continued scaling for increased productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The additional oxide protection layer effectively addresses leakage current problems by maintaining the integrity of epitaxial layers and reducing the impact of phosphorus residues, thereby enhancing the performance and reliability of semiconductor devices.
Implementation Method 1
a protection layer with an oxide material is additionally disposed on an epitaxial layer, to improve the leakage current issues
Implementation Method 2
a selective epitaxial growth (SEG) process is performed to form an epitaxial structure with the same lattice arrangement as that of the substrate, such as including a silicon germanium (SiGe) epitaxial layer
Implementation Method 3
Since the lattice constant of the SiGe layer is larger than the lattice constant of the substrate, accordingly, the compressive stress is then formed and applied to the channel region
Implementation Method 4
a silicon carbide (SiC) epitaxial layer may be optionally formed in the substrate of a N-type MOS (NMOS) transistor, to apply the tensile stress to the channel region
Implementation Method 5
if a tensile stress is needed to be applied, a silicon carbide (SiC) epitaxial layer may be optionally formed in the substrate of a N-type MOS (NMOS) transistor
Data Source
AI summary
A semiconductor device and method of fabricating the same include a substrate, a first epitaxial layer, a first protection layer, and a contact etching stop layer. The substrate includes a PMOS transistor region, and the first epitaxial layer is disposed on the substrate, within the PMOS transistor region. The first protection layer is disposed on the first epitaxial layer, covering surfaces of the first epitaxial layer. The contact etching stop layer is disposed on the first protection layer and the substrate, wherein a portion of the first protection layer is exposed from the contact etching stop layer.