PMOS Equalizer Layout for High Speed Memory Data Line Precharging
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Solution Overview
Problem
Conventional semiconductor memory devices using NMOS transistors for equalizers and sense amplifiers face challenges in precharging local data lines to equal voltages, leading to inefficiencies in data sensing and amplification, particularly during precharge and sensing periods.
Innovation Solution
The implementation of PMOS transistors in equalizers and differential amplifier type local data line sense amplifiers, allowing for more precise control and equal precharging of local data lines, and enhancing data sensing and amplification speeds without increasing chip size by integrating PMOS transistors into existing conjunction blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If NMOS transistors are used for equalizers and sense amplifiers, then the equalizer and sense amplifier can be disposed in the sense amplifier block to reduce memory cell core area, but the local data lines cannot be precharged to equal voltages consistently across all precharge periods
Solution Approach 1:
The patent changes the transistor type parameter from NMOS to PMOS for the equalizer circuit. PMOS transistors have different electrical characteristics including higher mobility for hole conduction and different threshold voltage behavior, which enables consistent precharging of local data lines to equal voltages across all precharge periods, resolving the reliability issue while maintaining area efficiency
2Device complexity
If NMOS transistors are used for equalizers and sense amplifiers, then device integration is achieved, but data access time is increased by approximately 250 ps
Solution Approach 1:
The patent changes the transistor type parameter from NMOS to PMOS in the equalizer circuit. PMOS transistors provide faster switching characteristics and better charge/discharge balance, reducing the equalization time and overall data access time by approximately 250 ps while maintaining device integration through the conjunction block layout
3Device complexity
If NMOS transistors are used for sense amplifiers, then the sense amplifier can be integrated in the sense amplifier block, but sensing speed is insufficient compared to differential amplification
Solution Approach 1:
The patent segments the sense amplifier circuit into two distinct functional blocks: the equalizer block containing PMOS transistors for precharging and equalizing local data lines, and the differential sense amplifier block for high-speed sensing. This segmentation allows each block to be optimized for its specific function while both are integrated into the overall memory device architecture
Solution Approach 2:
The patent implements dynamic control of the equalizer circuit using control signals (EQN1, EQN2) that activate the PMOS equalizer transistors at appropriate times during the memory operation cycle. This dynamic operation ensures proper timing of the equalization phase before sensing, optimizing both speed and integration
Data Source
AI summary
A memory device includes a memory cell array block including memory cells, a word line driver block adjacent the memory cell array block disposed in a direction in which word lines of the memory cells are arranged, a sense amplifier block adjacent the memory cell array block disposed in a direction in which bit lines of the memory cells are arranged, a conjunction block disposed at an intersection of the word line driver block and the sense amplifier block, an equalizer for equalizing a pair of local data lines, the equalizer disposed in the conjunction block, and a local data line sense amplifier configured to sense and amplify signals on a pair of local data lines, and having transistors of a first type disposed in the conjunction block and transistors of a second type disposed in the sense amplifier block.