PMOS FinFET Germanium Source Drain and Sidewall Modification
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Solution Overview
Problem
Current FinFET transistors, particularly PMOS devices, face challenges in achieving optimal efficiency and performance due to limitations in material composition and processing techniques, which affect carrier mobility and device complexity.
Innovation Solution
The development of a PMOS FinFET device with a fin structure and source/drain regions made of silicon germanium doped with p-type dopants, where the source/drain regions have a higher germanium concentration than the channel regions, and the fin sidewall is partially removed to expose the upper portion, enhancing carrier mobility and stress on the channel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the germanium concentration is increased in source/drain regions, then carrier mobility is improved, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The patent applies local quality by creating distinct germanium concentration zones: source/drain regions have higher germanium concentration (e.g., 10-50%) while channel regions have lower germanium concentration (e.g., 0-10%). This spatial differentiation of material composition optimizes carrier mobility in source/drain regions without compromising channel performance, resolving the contradiction between improving carrier mobility and maintaining manufacturing precision.
2Reliability
If the fin sidewall is partially removed to expose the upper portion, then carrier mobility and stress on channel are enhanced, but device complexity increases
Solution Approach 1:
The fin sidewall is segmented into two distinct regions: a lower portion that remains intact and an upper portion that is removed to expose the channel. This segmentation allows selective application of stress enhancement techniques to specific regions, improving carrier mobility while limiting the overall structural complexity increase.
Solution Approach 2:
The partial removal of fin sidewall creates localized exposure of the upper channel portion, applying stress enhancement precisely where needed for carrier mobility improvement without modifying the entire fin structure, thus balancing performance enhancement with device complexity management.
3Productivity
If the fin structure is modified to enhance stress on channel, then device performance is improved, but manufacturing complexity increases
Solution Approach 1:
The fin structure is divided into functional segments: the lower fin portion maintains structural integrity while the upper fin portion is modified to provide stress enhancement. This segmentation enables performance improvement through targeted modifications rather than complete restructuring, managing manufacturing complexity.
Solution Approach 2:
Stress enhancement features are applied locally to specific regions of the fin structure (e.g., upper portion sidewall removal, selective epitaxial growth) rather than uniformly across the entire structure, improving device performance while minimizing the increase in overall manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the carrier mobility and performance of PMOS FinFET devices by increasing the germanium concentration in source/drain regions and modifying the fin structure, leading to enhanced device efficiency and reduced defects.
Implementation Method 1
both the fin structure and the source/drain regions may include silicon germanium that is doped with a p-type dopant such as boron
Implementation Method 2
performing a plasma doping process on the fin structure, the plasma doping process introducing a dopant into the fin structure and the sidewall structure
Implementation Method 3
performing a plasma doping process on the fin structure, the plasma doping process introducing a dopant into the fin structure and the sidewall structure
Data Source
AI summary
A semiconductor device includes a fin structure disposed on a substrate, a shallow-trench isolation (STI) region on opposite sides of the fin structure, dielectric fin sidewall structures extending along sides of the fin structure and extending from a top of the STI region partially up the fin structure, and a source/drain region disposed within an upper portion of the fin structure. A bottom surface of the source/drain region contacts a top surface of the dielectric fin sidewall.