PMOS Gate Bias Switching for Standby Leakage Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing electronic circuits, particularly those in RF applications, face high leakage currents during standby mode, leading to battery drain and reduced battery life due to the inability of prior art circuits to effectively control the gate voltage of PMOS devices, resulting in undesired power dissipation and potential overvoltage conditions.
Innovation Solution
A circuital arrangement and method that includes a voltage switching circuit to selectively control the gate-to-source voltage of PMOS devices, extending the control voltage range beyond the supply voltage during standby mode, and using a voltage switching circuit to couple higher voltages to the error amplifier output, thereby reducing leakage current while maintaining output voltage regulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the gate voltage of PMOS devices is controlled using conventional circuits during standby mode, then the circuit structure remains simple, but high leakage currents occur leading to battery drain
Solution Approach 1:
The patent implements dynamic gate voltage control by switching between two voltage sources (VDD and VBOOT) based on operational mode. During standby mode, the circuit dynamically applies higher gate voltage (VBOOT) to reduce leakage current, while during active mode it uses conventional voltage (VDD). This dynamic adaptation resolves the contradiction by adjusting circuit behavior according to operational requirements.
Solution Approach 2:
The patent changes the gate voltage parameter from the conventional VDD level to a higher VBOOT level during standby mode. This parameter change enables the PMOS devices to operate in a regime with significantly reduced leakage current. The bootstrapping mechanism generates this elevated voltage parameter dynamically, resolving the energy loss issue without requiring a complete circuit redesign.
2Loss of energy
If higher gate voltage is applied to reduce leakage current during standby mode, then leakage current is reduced, but the risk of overvoltage conditions increases
Solution Approach 1:
The patent introduces a bootstrapping circuit as an intermediary mechanism that safely generates and applies the elevated gate voltage. This intermediary circuit includes voltage clamping elements and controlled switching that prevent direct application of excessive voltage to sensitive components. The bootstrapping circuit acts as a buffer that enables high gate voltage for leakage reduction while maintaining reliability through controlled voltage application.
Solution Approach 2:
The patent applies the elevated gate voltage (VBOOT) only during standby mode when high current drive is not required, and switches back to conventional voltage (VDD) during active mode. This preliminary selection of operating conditions ensures that the higher voltage is applied only when beneficial for leakage reduction, preventing overvoltage damage during active operation when full current drive capability is needed.
3Loss of energy
If conventional LDO regulator circuits are used, then output voltage regulation is maintained, but leakage current during standby mode remains high causing battery drain
Solution Approach 1:
The patent implements periodic switching between two operational states: standby mode with elevated gate voltage for minimal leakage, and active mode with conventional gate voltage for full performance. The control circuit periodically monitors the operational state and switches between voltage regimes accordingly. This periodic adaptation resolves the contradiction by optimizing power consumption for each operational phase.
Solution Approach 2:
The patent dynamically adjusts the gate voltage level based on the operational mode detected by the control circuit. During standby periods, the system dynamically switches to VBOOT for minimal leakage. During active periods requiring high current, it dynamically returns to VDD. This dynamic behavior enables the system to minimize battery power consumption during standby while maintaining full functionality during active operation, directly resolving the battery life contradiction.
Data Source
AI summary
Various methods and circuital arrangements for leakage reduction in MOS devices are presented. A pull-up circuit is selectively coupled to a gate of the MOS device to provide control of a voltage to the gate that is larger than a source voltage. Voltage switching circuits selectively couple different voltages to the body and/or back-gate terminals of the MOS device. During a standby mode of operation, the leakage current of the MOS device is decreased by driving the MOS device further into its subthreshold leakage region. During standby mode, a threshold voltage of the MOS device is increased by coupling a voltage higher than the source voltage to the body and/or back-gate terminals. The MOS device can be a pass device used in low dropout regulator (LDO). During standby mode, the LDO maintains output regulation by driving the MOS device further into its subthreshold leakage region and/or increasing the threshold voltage.