Dummy PMOS Gate Protection via Carbon-Doped Layer
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Solution Overview
Problem
In metal-gate CMOS processes, the corners of dummy PMOS gates with thinner cap layers are exposed during the salicide process, leading to dummy gate residue due to reaction with metal, which is not effectively prevented by existing methods.
Innovation Solution
A method involving the formation of a carbon-doped protective layer with a low etching rate on the dummy PMOS gates, along with a blocking layer and spacer formed from the same precursor, prevents corner exposure by maintaining the cap layer thickness and avoiding reaction with metal during the salicide process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a standard cap layer is formed on dummy gates, then the fabrication process is simplified, but the corner of the dummy gate with thinner cap layers is exposed and reacts with metal to cause dummy gate residue
Solution Approach 1:
The patent applies different cap layer thicknesses to different regions: the first cap layer has a first thickness on NMOS dummy gates, while the second cap layer has a second thickness (greater than the first) on PMOS dummy gates. This local differentiation prevents corner exposure and metal reaction on PMOS gates without complicating the overall fabrication process
Solution Approach 2:
The patent performs preliminary protective action by forming the thicker second cap layer on PMOS dummy gates before the salicide process. This preemptive measure ensures that the cap layer corners are sufficiently thick to prevent exposure and subsequent metal reaction during later fabrication steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively prevents dummy gate residue in the gate replacement process by ensuring the corner of the dummy PMOS gate is not exposed, maintaining the cap layer's capping effect and preventing reaction with metal, thus ensuring reliable semiconductor device fabrication.
Implementation Method 1
such protective layer has a low etching rate, the corner of the dummy gate in the second stack is not exposed in the later removal process
Data Source
AI summary
A method for fabricating a semiconductor device is described. A gate layer, a C-doped first protective layer and a hard mask layer are formed on a substrate and then patterned to form a first stack in a first area and a second stack in a second area. A second protective layer is formed on the sidewalls of the first and the second stacks. A blocking layer is formed in the first area and a first spacer formed on the sidewall of the second protective layers on the sidewall of the second stack in the second area. A semiconductor compound is formed in the substrate beside the first spacer. The blocking layer and the first spacer are removed. The hard mask layer in the first stack and the second stack is removed.