PMOS Gate Contact Plug Layout to Reduce Metal Boundary Effects
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Solution Overview
Problem
The issue of metal boundary effects during the fabrication of CMOS devices due to overlapping work function metal layers from NMOS and PMOS regions is not adequately addressed in current semiconductor technology, leading to inferior device performance.
Innovation Solution
The position of the gate contact plug is adjusted during CMOS transistor fabrication, specifically landing it directly on the PMOS region and away from the boundary with the NMOS region, using a metal gate structure that extends continuously between these regions, thereby minimizing the overlap of work function metal layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If work function metal layers from NMOS and PMOS regions are overlapped during CMOS fabrication, then continuous metal gate structure can be formed, but metal boundary effects occur causing inferior device performance
Solution Approach 1:
The patent divides the metal gate structure into two separate work function metal layers: a first work function metal layer for the NMOS region and a second work function metal layer for the PMOS region. These layers are formed in different processing steps and are spatially separated, preventing the metal boundary effects that occur when work function metal layers from NMOS and PMOS regions overlap. This segmentation maintains the continuous metal gate structure while eliminating the harmful boundary effects.
2Ease of manufacture
If polysilicon is used as gate electrode material, then fabrication process is simple, but boron penetration and depletion effect reduce gate capacitance and driving force
Solution Approach 1:
The patent changes the material parameter of the gate electrode from polysilicon to metal materials with different work functions. The first work function metal layer has a work function suitable for NMOS (lower work function) and the second work function metal layer has a work function suitable for PMOS (higher work function). This material substitution eliminates boron penetration and depletion effects while maintaining fabrication simplicity through standard metal deposition processes.
Data Source
AI summary
A semiconductor device including a substrate having a NMOS region and a PMOS region; a metal gate extending continuously along a first direction from the NMOS region to the PMOS region on the substrate; a first source/drain region extending along a second direction adjacent to two sides of the metal gate on the NMOS region; a second source/drain region extending along the second direction adjacent to two sides of the metal gate on the PMOS region; a first contact plug landing on the second source/drain region adjacent to one side of the metal gate; a second contact plug landing on the second source/drain region adjacent to another side of the metal gate; and a third contact plug landing directly on a portion of the metal gate on the PMOS region and between the first contact plug and the second contact plug.