PMOS Gate Electrode Counter-Doping for SRAM Write Margin
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Solution Overview
Problem
The scaling of semiconductor devices leads to severe degradation of carrier mobility, particularly in PMOS devices, resulting in unbalanced drive currents between PMOS and NMOS devices in SRAM cells, causing writing issues and degraded write margins due to high drive currents of PMOS devices.
Innovation Solution
The introduction of counter-doping in the gate electrode of PMOS devices with a higher concentration of n-type impurities, specifically greater than 1×10^19/cm^3, to balance the performance of PMOS and NMOS devices by modifying the work function and reducing drive currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SiGe stressors are grown in PMOS source and drain regions to improve carrier mobility, then PMOS drive current increases, but write margins degrade and writing becomes unreliable
Solution Approach 1:
The patent modifies the work function of the PMOS gate electrode by changing its doping concentration from conventional p-type to n-type with concentration greater than 1×10^19/cm³. This parameter change in the gate electrode composition directly adjusts the threshold voltage and drive current characteristics of the PMOS device, enabling write margin improvement while maintaining adequate drive current
Solution Approach 2:
The patent inverts the conventional doping approach for PMOS gate electrodes. Instead of using p-type doping as is standard for PMOS devices, the patent applies n-type doping to the gate electrode, which is normally used for NMOS devices. This inversion of the doping type allows for precise control of PMOS drive current to balance performance with NMOS devices and improve write margins
2Productivity
If device scaling continues to improve density and cost, then integration density increases, but carrier mobility degrades severely
Solution Approach 1:
The patent changes the physical and electrical parameters of the gate electrode by introducing n-type doping with high concentration (>1×10^19/cm³). This parameter modification alters the work function and electric field distribution in the channel, compensating for mobility degradation caused by scaling effects such as increased scattering and reduced channel dimensions
Solution Approach 2:
The patent applies preliminary counter-doping to the gate electrode before final device operation. By pre-adjusting the gate electrode doping to n-type, the patent anticipates and counteracts the mobility degradation that will occur during device scaling, establishing optimized electrical characteristics before the device is put into service
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances write margins and reliability by reducing PMOS drive currents, improving write speed and reducing leakage currents, while maintaining peripheral circuit performance without additional process complexities.
Implementation Method 1
The introduction of counter-doping in the gate electrode of PMOS devices with a higher concentration of n-type impurities, specifically greater than 1×10^19/cm^3, to balance the performance of PMOS and NMOS devices by modifying the work function
Data Source
AI summary
A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semiconductor substrate, a gate electrode on the gate dielectric wherein the gate electrode comprises a p-type impurity and an n-type impurity, and a stressor formed in a source/drain region. The device drive current of the pull-up PMOS device is reduced due to the counter-doping of the gate electrode.