Gate Driver Using PMOS Transistors to Reduce Dead Space
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Solution Overview
Problem
Existing gate drivers in display devices face issues with increased dead space due to the use of NMOS transistors, which lead to reduced operational reliability and increased transistor size, necessitating bootstrapping operations to manage voltage levels.
Innovation Solution
The gate driver is designed with PMOS transistors for the carry output and gate output circuits, incorporating a delay circuit, voltage limiting circuit, and inverter circuit to manage gate signal voltages, reducing the need for bootstrapping and minimizing dead space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If NMOS transistors are used in the carry output circuit and gate output circuit, then the threshold voltage shifts in a negative direction, but this decreases operational reliability and increases transistor size
Solution Approach 1:
The patent inverts the transistor type used in the carry output circuit and gate output circuit from NMOS to PMOS. This inversion prevents the negative threshold voltage shift that occurs with NMOS transistors, thereby improving operational reliability and reducing the need for larger transistor sizes to compensate for mobility issues.
2Productivity
If NMOS transistors are used in the carry output circuit and gate output circuit, then the mobility is reduced, but this increases the size of the transistors and the dead space of the gate driver
Solution Approach 1:
The patent switches from NMOS to PMOS transistors in the carry output circuit and gate output circuit. PMOS transistors have higher mobility than NMOS transistors, which reduces the required transistor size and consequently minimizes the dead space in the gate driver circuit.
3Area of stationary object
If PMOS transistors are used in the carry output circuit and gate output circuit, then the dead space is reduced, but the voltage levels must be carefully managed
Solution Approach 1:
The patent introduces a voltage limiting circuit as an intermediary component between the PMOS transistors in the carry output circuit and gate output circuit. This voltage limiting circuit manages the voltage levels by constraining them within safe ranges, thereby reducing the complexity of voltage management while maintaining the benefits of using PMOS transistors.
Data Source
AI summary
A gate driver includes stages including a delay circuit for receiving an input signal responsive to a clock signal and outputting the input signal to a control node, a voltage limiting circuit for limiting a voltage of the control node based on high and low limit voltages, an inverter circuit for inverting and outputting the voltage of the control node to an inverting control node, a carry output circuit for outputting a first low gate voltage to a carry output node and outputting a first high gate voltage to the carry output node responsive to the voltage of the inverting control node and a gate output circuit for outputting a second low gate voltage that is lower than the first low gate voltage to a gate output node and outputting a second high gate voltage that is higher than the first high gate voltage to the gate output node.