Selective Fluorine Injection for PMOS Gate Insulator Thickness Control
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Solution Overview
Problem
In CMOS devices, the gate leakage current is higher in NMOS regions than in PMOS regions due to differences in charge mobility, and modifying the thickness of gate insulating layers between these regions is complex, leading to increased manufacturing costs and integration limitations.
Innovation Solution
A method involving selective fluorine injection into PMOS regions to form thinner oxynitride-based gate insulating layers, with subsequent high-k dielectric layers, allowing for distinct thickness control and reduced leakage currents, using rapid thermal processing and ion beam doping techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the width of the PMOS region is increased to improve transistor channel current, then the transistor channel current in the PMOS region is improved, but the integration of the CMOS device is limited
Solution Approach 1:
The patent applies local quality by forming a thinner gate insulating layer specifically in the PMOS region while maintaining a thicker gate insulating layer in the NMOS region. This is achieved by selectively injecting fluorine ions into the PMOS region before gate insulating layer formation, which creates a localized modification that allows the PMOS transistor to achieve higher channel current without increasing the overall device area, thus resolving the contradiction between improving transistor performance and maintaining device integration.
2Power
If a thinner gate insulating layer is formed for the PMOS region to improve transistor channel current, then the transistor channel current is improved, but the manufacturing process becomes complicated and costs increase
Solution Approach 1:
The patent employs preliminary action by injecting fluorine ions into the PMOS region before forming the gate insulating layer. This pre-treatment modifies the substrate in the PMOS region to facilitate the formation of a thinner gate insulating layer during the subsequent oxidation process. By performing this preparatory step beforehand, the patent avoids the need for complex post-formation thickness modification processes such as selective etching or patterning, thereby simplifying the overall manufacturing process while still achieving the desired differential gate insulating layer thicknesses.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of thinner gate insulating layers in PMOS regions while maintaining good electric characteristics, reducing leakage currents and manufacturing costs, and improving transistor channel currents without complicating the patterning process.
Implementation Method 1
selectively injecting fluorine (F) into a first region on a substrate
Implementation Method 2
The forming of the first gate insulating layer may be performed in an atmosphere containing NO by applying a rapid thermal processing (RTP)
Data Source
AI summary
Provided is a method of manufacturing a semiconductor device, in which the thickness of a gate insulating layer of a CMOS device can be controlled. The method can include selectively injecting fluorine (F) into a first region on a substrate and avoiding injecting the fluorine (F) into a second region on the substrate. A first gate insulating layer is formed of oxynitride layers on the first and second regions to have first and second thicknesses, respectively, where the first thickness is less than the second thickness. A second gate insulating layer is formed on the first gate insulating layer and a gate electrode pattern is formed on the second gate insulating layer.