PMOS Gate Contact Plug Placement for Metal Boundary Mitigation
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Solution Overview
Problem
The conventional polysilicon gate in semiconductor devices faces issues such as boron penetration and depletion effects, leading to reduced gate capacitance and driving force, while the metal boundary effect during CMOS device fabrication poses a challenge due to overlapping work function metal layers from NMOS and PMOS regions.
Innovation Solution
A semiconductor device design where a metal gate extends continuously from the NMOS to the PMOS region, with strategically positioned contact plugs, including a third contact plug landing directly on the PMOS region, between or away from the boundary separating the NMOS and PMOS regions, to mitigate the metal boundary effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If work function metal layers are overlapped from NMOS and PMOS regions during CMOS device fabrication, then continuous metal gate can be formed, but metal boundary effect occurs due to overlapping
Solution Approach 1:
The patent segments the contact plug structure into multiple types: first contact plugs connecting to source/drain regions, second contact plugs connecting to gate structures in NMOS region, and third contact plugs connecting to gate structures in PMOS region. This segmentation allows independent optimization of each contact type to avoid metal boundary effects while maintaining continuous gate formation
Solution Approach 2:
The patent applies different contact plug configurations to different regions: in NMOS region, second contact plugs are used with specific positioning, while in PMOS region, third contact plugs are used with different positioning strategies. This local differentiation resolves metal boundary effects by adapting the contact structure to the specific requirements of each transistor type
2Reliability
If contact plugs are positioned to avoid metal boundary effect, then device performance improves, but manufacturing complexity increases
Solution Approach 1:
The patent uses a unified interlayer dielectric structure and common fabrication processes for all contact plugs, while differentiating only the contact plug positioning and connection targets. This universal approach simplifies manufacturing by maintaining process consistency while achieving region-specific optimization through strategic contact placement
Data Source
AI summary
A semiconductor device including a substrate having a NMOS region and a PMOS region; a metal gate extending continuously along a first direction from the NMOS region to the PMOS region on the substrate; a first source/drain region extending along a second direction adjacent to two sides of the metal gate on the NMOS region; a second source/drain region extending along the second direction adjacent to two sides of the metal gate on the PMOS region; a first contact plug landing on the second source/drain region adjacent to one side of the metal gate; a second contact plug landing on the second source/drain region adjacent to another side of the metal gate; and a third contact plug landing directly on a portion of the metal gate on the PMOS region and between the first contact plug and the second contact plug.