PMOS Metal Gate Contact Plug Layout for Metal Boundary Mitigation
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Solution Overview
Problem
The conventional polysilicon gate in semiconductor devices faces issues such as boron penetration and depletion effects, leading to reduced gate capacitance and driving force, while the metal boundary effect from overlapping work function metal layers in CMOS devices is a significant fabrication challenge.
Innovation Solution
A semiconductor device design where a metal gate extends continuously from the NMOS region to the PMOS region, with strategically positioned contact plugs, including a third contact plug landing directly on the PMOS region, between or away from the boundary separating the NMOS and PMOS regions, to mitigate the metal boundary effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If work function metal layers from NMOS region and PMOS region are overlapped during CMOS fabrication, then continuous metal gate can be formed, but metal boundary effect occurs
Solution Approach 1:
The patent divides the contact plug configuration into segments: first and second contact plugs connect to source/drain regions, while a third contact plug specifically connects to the metal gate on the PMOS region. This segmentation allows independent control of contact positions to mitigate metal boundary effects while maintaining continuous gate formation
Solution Approach 2:
The patent applies different contact plug arrangements to different regions: on the NMOS region, contact plugs connect to source/drain regions, while on the PMOS region, a contact plug connects directly to the metal gate. This local differentiation resolves metal boundary effects in specific regions without compromising overall device performance
2Ease of manufacture
If polysilicon is used as gate material, then gate electrode can be fabricated, but boron penetration and depletion effects occur
Solution Approach 1:
The patent changes the material parameter from polysilicon to metal for the gate electrode, fundamentally altering the electrical properties to eliminate boron penetration and depletion effects while maintaining manufacturability through established metal deposition processes
Data Source
AI summary
A semiconductor device including a substrate having a NMOS region and a PMOS region; a metal gate extending continuously along a first direction from the NMOS region to the PMOS region on the substrate; a first source/drain region extending along a second direction adjacent to two sides of the metal gate on the NMOS region; a second source/drain region extending along the second direction adjacent to two sides of the metal gate on the PMOS region; a first contact plug landing on the second source/drain region adjacent to one side of the metal gate; a second contact plug landing on the second source/drain region adjacent to another side of the metal gate; and a third contact plug landing directly on a portion of the metal gate on the PMOS region and between the first contact plug and the second contact plug.