PMOS Gate Spacer Compressive Stress via Ion Implantation
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Solution Overview
Problem
The manufacturing of PMOS devices with compressive channel layers is complex and costly due to the need for additional oxidation processes and increased leakage current caused by Si—Ge layers, which also degrade device performance at reduced sizes.
Innovation Solution
A method involving the formation of a buffer oxide layer, a silicon nitride layer, and impurity implantation to create compressive stress in the channel layer, using Ge as the impurity to improve carrier mobility without the need for additional oxidation processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a Si—Ge layer is used to apply compressive stress to improve carrier mobility, then the mobility of carrier is improved, but the manufacturing process becomes more complex and costly due to additional oxidation processes
Solution Approach 1:
The patent changes the material parameter from Si-Ge to silicon nitride, and applies impurity implantation instead of epitaxial growth. This substitution maintains the compressive stress function while eliminating the need for additional oxidation processes, thereby reducing manufacturing complexity
Solution Approach 2:
The patent uses a temporary silicon nitride layer that is implanted with impurities to generate compressive stress, then removed after serving its purpose. This disposable approach avoids the complexity of forming permanent Si-Ge layers while achieving the same stress application effect
2Reliability
If a Si—Ge layer is used to apply compressive stress to improve carrier mobility, then the mobility of carrier is improved, but the manufacturing cost increases due to additional oxidation processes
Solution Approach 1:
The patent substitutes the Si-Ge material system with silicon nitride and changes the stress application method from epitaxial growth to impurity implantation. This parameter change eliminates additional oxidation processes, directly reducing manufacturing costs while maintaining carrier mobility improvement
Solution Approach 2:
The patent extracts and removes the oxidation process from the manufacturing sequence by using impurity implantation instead. This extraction eliminates the costly and time-consuming oxidation step while preserving the essential function of applying compressive stress to improve carrier mobility
3Reliability
If a Si—Ge layer is used to apply compressive stress, then the mobility of carrier is improved, but leakage current increases due to reduced band gap
Solution Approach 1:
The patent changes the material parameter from Si-Ge (which reduces band gap) to silicon nitride with impurity implantation. This parameter change maintains the compressive stress effect for improving carrier mobility while avoiding the band gap reduction that causes increased leakage current
4Productivity
If device size is reduced to increase integration, then the speed of device increases, but driving current and breakdown voltage are reduced
Solution Approach 1:
The patent applies compressive stress locally to the channel region through the silicon nitride layer and impurity implantation. This localized stress enhancement improves carrier mobility specifically in the channel area, allowing smaller device dimensions to maintain or increase driving current despite overall size reduction
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method simplifies the manufacturing process, reduces costs, and enhances PMOS device performance by increasing driving current without altering the gate threshold voltage or increasing leakage current.
Implementation Method 1
The compressive stress imparted on the silicon nitride layer due to the implantation of impurities is transmitted to the substrate under the silicon nitride layer to compress a channel layer or region in the silicon substrate under the gate electrode
Implementation Method 2
implanting impurities into the silicon nitride layer
Data Source
AI summary
A method of forming a compressive channel layer in a PMOS device and a PMOS device having a compressive channel layer are provided. The method includes (a) forming a buffer oxide layer on a silicon semiconductor substrate having a gate oxide layer and a gate electrode thereon, (b) forming a silicon nitride layer on the buffer oxide layer, (c) implanting impurities into the silicon nitride layer, and (d) etching or patterning the silicon nitride layer and the buffer oxide layer into which impurities are implanted to form gate spacers on sidewalls of the gate electrode.