PMOS Gate Stack Buffer Layer for Oxygen Diffusion
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Solution Overview
Problem
The challenge in manufacturing high-k gate dielectric/metal gate semiconductor devices is to lower the PMOS threshold voltage without damaging the gate dielectric layer, gate electrode, and source/drain regions, as high-temperature processes introduce oxygen vacancies and increase PMOS threshold voltage, and existing methods like oxygen diffusion through sidewall spacer removal are difficult to control and damaging.
Innovation Solution
A method involving the formation of a semiconductor device with a buffer layer of low-k dielectric material on the PMOS region's gate stack, allowing oxygen diffusion from an annealing environment into the high-k gate dielectric layer, thereby lowering the PMOS threshold voltage without affecting the NMOS region or causing damage, by forming a first gate stack in the NMOS region and a second gate stack in the PMOS region with a low-k buffer layer and sidewall spacers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-temperature processes are used during integration, then the metal gate and high-k insulating material interface is formed, but oxygen vacancies are introduced into the high-k gate dielectric material causing PMOS threshold voltage increase and device reliability deterioration
Solution Approach 1:
The patent applies preliminary action by performing oxygen diffusion annealing at a lower temperature (400-600°C) after device fabrication to fill oxygen vacancies in the high-k gate dielectric material. This post-fabrication treatment restores the PMOS threshold voltage without requiring high-temperature processes that would damage other device components, thus improving reliability while avoiding the harmful effects of high-temperature processing.
2Ease of operation
If oxygen diffusion is performed by removing sidewall spacer, then PMOS threshold voltage is lowered, but the gate dielectric layer, gate electrode, and source/drain regions are damaged
Solution Approach 1:
The patent applies parameter changes by modifying the annealing temperature parameter to 400-600°C, which is sufficiently high to enable oxygen diffusion into the high-k gate dielectric material but low enough to prevent damage to the gate dielectric layer, gate electrode, and source/drain regions. This temperature optimization allows effective PMOS threshold voltage control while avoiding device damage that occurs with higher temperature processes or sidewall spacer removal methods.
3Reliability
If oxygen diffusion is performed at high temperature, then oxygen vacancies are filled in high-k gate dielectric material, but damage occurs to gate dielectric layer, gate electrode, and source/drain regions
Solution Approach 1:
The patent applies parameter changes by optimizing the annealing temperature to the range of 400-600°C, which is sufficiently high to enable effective oxygen diffusion and fill oxygen vacancies in the high-k gate dielectric material, yet low enough to prevent damage to the gate dielectric layer, gate electrode, and source/drain regions. This temperature optimization resolves the contradiction between achieving reliability improvement through oxygen vacancy filling and avoiding thermal damage to device components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively lowers the PMOS threshold voltage while maintaining the integrity of the device, enhancing overall performance by allowing controlled oxygen diffusion through a low-k buffer layer, which avoids damage to the gate and substrate, and maintains the NMOS threshold voltage.
Implementation Method 1
annealing the device in an oxygen environment, such that oxygen in the oxygen environment being diffused into the second high-k gate dielectric layer of the second gate stack through the buffer layer
Data Source
AI summary
The present invention relates to a semiconductor device and a manufacturing method for making the same, wherein, according to the method, after the gate stack is formed, a buffer layer is formed on sidewalls of an PMOS gate stack, the buffer layer being formed of a porous low-k dielectric layer; and then, sidewall spacers and source/drain/halo regions, and source and drain regions are formed for the device; and finally, a high-temperature anneal is conducted in an oxygen environment such that the oxygen in the oxygen environment diffuse through the buffer layer into the high-k dielectric layer of the second gate stack. The present invention lowers threshold voltage of the PMOS device without affecting the threshold voltage of the NMOS device, avoids damages to the gate and substrate incurred by removing the PMOS sidewall spacer in a traditional process, and hereby effectively improves the overall performance of the device.