pMOS Gate Stack With Dipole Capping for Low Thermal-Budget NBTI
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Solution Overview
Problem
Existing MOSFET transistors face issues with bias temperature instability (BTI) due to defects in the dielectric stack, particularly in pMOS devices, which are exacerbated by high-temperature anneals incompatible with advanced CMOS technologies like sequential 3D integration and Ge/III-V channel technologies.
Innovation Solution
A gate stack design for pMOS transistors featuring a silicon oxide dielectric interlayer of 0.5-1 nm thickness, a high-k dielectric layer, and a first dipole-forming capping layer (e.g., Al2O3) in direct contact with the interlayer, shifting the high-k bandgap relative to the substrate's valence band, eliminating the need for high-temperature anneals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-temperature reliability anneal (>800°C) is applied after gate stack deposition, then pMOS NBTI reliability is improved, but thermal budget is exceeded making it incompatible with advanced CMOS technologies
Solution Approach 1:
The dipole-forming capping layer is deposited on the dielectric interlayer before high-k dielectric deposition, pre-configuring the interface to minimize trap formation and eliminate the need for subsequent high-temperature reliability anneal
Solution Approach 2:
The dipole-forming capping layer acts as an intermediary between the dielectric interlayer and high-k dielectric, creating favorable energy band alignment that prevents trap formation without requiring thermal processing
2Reliability
If dipole-forming capping layer is introduced to shift high-k bandgap, then reliability is improved without high-temperature anneal, but device complexity increases
Solution Approach 1:
The dipole-forming capping layer modifies the energy band parameters (bandgap alignment, work function) of the interface between dielectric interlayer and high-k dielectric, enabling reliability improvement through electronic structure optimization rather than thermal processing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances pMOS NBTI reliability without high-temperature anneals, enabling further scaling and performance improvements in CMOS technologies by making traps in the high-k layer dominant, thus maintaining reliability while adhering to low thermal budgets.
Implementation Method 1
a first dipole-forming capping layer between the dielectric interlayer and the high-k dielectric layer and in direct contact with the dielectric interlayer, for shifting down the bandgap of the high-k dielectric layer with relation to the valence band of the substrate
Data Source
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AI summary
A p-channel metal-oxide-semiconductor transistor comprising a gate stack (100) which comprises: a silicon oxide comprising dielectric interlayer (120) on a substrate (110), wherein the dielectric interlayer (120) has a thickness below 1nm; a high-k dielectric layer (140) having a higher dielectric constant compared to the dielectric interlayer (120); a first dipole-forming capping layer (130) between the dielectric interlayer (120) and the high-k dielectric layer (140) and in direct contact with the dielectric interlayer (120), for shifting down a high-K bandgap of the high-k dielectric layer with relation to a valence band of the substrate (110), wherein the first dipole-forming capping layer (130) has a thickness below 2nm; at least one work function metal above the high-k dielectric layer.