PMOS HKMG Gate Stack with Dipole Depinning for Vfb Rolloff

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Solution Overview

Problem

The challenge of achieving desired bandedge performance in PMOS high-κ metal gate (HKMG) stacks is exacerbated by significant flatband voltage (Vfb) rolloff due to Fermi level pinning, which is difficult to address in advanced device scaling.

Innovation Solution

A method involving the deposition of an interfacial layer, high-κ dielectric layer, dipole depinning layer, P-metal layer, and capping layer is performed in situ within an integrated processing system, including low temperature oxygen and nitrogen annealing processes, to enhance bandedge performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If conventional PMOS HKMG stack manufacturing is used, then device scaling is achieved, but flatband voltage rolloff occurs due to Fermi level pinning

Engineering Contradiction:

Improvedevice geometry sizeVSAvoidflatband voltage performance

Core Design Contradiction:

Length of moving objectVSReliability

Solution Approach 1:

An intermediary dipole layer is introduced between the high-κ dielectric layer and the P-metal gate layer. This dipole layer acts as a mediator that compensates for Fermi level pinning at the semiconductor-dielectric interface, thereby correcting flatband voltage rolloff while enabling continued device scaling. The dipole layer creates an electric field that offsets the unwanted voltage shift caused by interface states.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The gate stack is constructed as a composite structure comprising multiple materials: high-κ dielectric material (such as hafnium oxide), dipole layer material (such as tungsten oxide or molybdenum oxide), and P-metal gate material. This composite material approach allows simultaneous optimization of dielectric properties, dipole moment for voltage control, and metal work function for threshold voltage tuning.

Inventive Principle:

Principle #40Composite materials

2Manufacturing precision

If multiple deposition steps for P-dipole and P-metal materials are performed separately, then precise control is achieved, but process complexity and cost increase

Engineering Contradiction:

Improvelayer deposition controlVSAvoidintegration process steps

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The deposition processes for P-dipole material and P-metal gate material are merged into a single integrated processing step within the same reaction chamber. This combining approach maintains precise control over layer formation while eliminating intermediate transfer steps, reducing process complexity, and lowering manufacturing costs. The sequential deposition occurs without breaking vacuum or transferring wafers between chambers.

Inventive Principle:

Principle #5Merging (Combining)

3Reliability

If dipole removal step is included, then precise voltage control is achieved, but process steps and costs increase

Engineering Contradiction:

Improvevoltage control precisionVSAvoidintegration flow efficiency

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The dipole layer is designed to be self-terminating or self-regulating, forming only the necessary thickness and providing sufficient dipole moment compensation without requiring subsequent removal or modification steps. The layer naturally saturates its dipole formation, eliminating the need for additional processing while maintaining precise voltage control.

Inventive Principle:

Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves flatband voltage (Vfb) by over 100 mV and minimizes capacitive effective thickness (CET) penalty, simplifying the integration flow and reducing costs by combining P-dipole and P-metal material deposition without a dipole removal step.