PMOS Headswitch Gate Biasing for Leakage Reduction

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Solution Overview

Problem

Conventional power gating systems experience significant leakage current even when transistors are turned off, leading to reduced battery life due to the non-ideal switching behavior of P-channel Metal Oxide Semiconductor (PMOS) headswitches, which allow leakage current to flow.

Innovation Solution

Implementing a super-cut off state for PMOS headswitches by maintaining a positive gate-source voltage when off, and adjusting the gate-source voltage to zero when the source voltage exceeds a threshold, using a voltage generator to select the control voltage from a second power supply in response to the first power supply's voltage level, thereby reducing gate-induced drain leakage (GIDL).

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If a PMOS headswitch is turned off to power collapse a part of the processing core, then power consumption is reduced, but leakage current still flows through the transistor

Engineering Contradiction:

Improvepower consumptionVSAvoidleakage current

Core Design Contradiction:

Loss of energyVSObject-generated harmful factors

Solution Approach 1:

The patent applies parameter changes by adjusting the gate-source voltage of the PMOS headswitch from the conventional zero voltage (when off) to a positive voltage level. This parameter change transforms the transistor into a super-cut-off state, significantly reducing leakage current while maintaining the power collapse function. The voltage generator dynamically adjusts the gate voltage based on the source voltage level to optimize leakage reduction.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If a PMOS headswitch is kept in conventional off state with zero gate-source voltage, then the transistor is turned off, but leakage current flows due to non-ideal switching behavior

Engineering Contradiction:

Improveswitching behaviorVSAvoidleakage current

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent implements preliminary anti-action by proactively applying a positive gate-source voltage to the PMOS headswitch before and during the off state. This preemptive measure counteracts the inherent leakage current that would otherwise flow in conventional off-state operation. The voltage generator continuously monitors and adjusts the gate voltage to maintain the super-cut-off condition, preventing leakage before it becomes problematic.

Inventive Principle:

Principle #9Preliminary anti-action

3Object-generated harmful factors

If voltage is adjusted to super-cut off state to reduce leakage, then leakage current is reduced, but additional voltage control circuitry is required

Engineering Contradiction:

Improveleakage currentVSAvoidvoltage control circuitry

Core Design Contradiction:

Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The voltage generator circuit is designed to automatically monitor the source voltage level and self-adjust the gate-source voltage of the PMOS headswitch accordingly. When the source voltage exceeds a reference threshold, the generator automatically applies the positive gate voltage to achieve super-cut-off state. This self-service mechanism reduces the need for complex external control circuitry while maintaining effective leakage reduction.

Inventive Principle:

Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach significantly reduces leakage current by maintaining the transistor in a super-cut off state or a zero gate-source voltage state, leading to increased battery life and reduced power consumption without increasing silicon area overhead.

Implementation Method 1

adjusting the gate-source voltage to be approximately zero, so that the transistor is held in an off state, though not in super-cut off... reducing leakage current by maintaining the transistor in a super-cut off state or a zero gate-source voltage state... reduced power consumption

Methodology Applied

Scientific EffectGate-induced drain leakage (GIDL):

Data Source

PatentUS11237580B1Systems and methods providing leakage reduction for power gated domains

Publication Date: 2022.02.01 QUALCOMM INC

AI summary

A system includes: a first power supply; a second power supply; a headswitch disposed between the first power supply and logic circuitry; an enable driver coupling the second power supply to a control terminal of the headswitch; and a voltage generator operable to adjust a control voltage from the second power supply to the control terminal of the headswitch in response to a first voltage level of the first power supply exceeding a reference voltage level.