PMOS LDO Fast-Slow Loop Topology for Full-Spectrum PSRR
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional LDOs either require an additional higher voltage supply for biasing the error amplifier or suffer from poor power supply ripple rejection ratio (PSRR) at mid-range frequencies, necessitating larger load capacitors that increase the size of the LDO.
Innovation Solution
A PMOS output LDO is designed with a fast loop and a slow loop configuration, where the fast loop includes a pass transistor, a noise cancelling transistor, and a source follower transistor to improve PSRR, and the slow loop includes an error amplifier, a source follower transistor, and a feedback resistor to maintain stability and provide a regulated output voltage without additional voltage supplies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional n-type output LDO is used to achieve good PSRR and faster transient response, then power supply ripple rejection ratio is improved, but an additional higher voltage supply is required which increases device complexity
Solution Approach 1:
The LDO circuit uses its own input voltage to bias the error amplifier through the pass transistor, eliminating the need for an external higher voltage supply. The pass transistor acts as a voltage buffer that provides the necessary bias voltage to the error amplifier from the input voltage itself, making the circuit self-sufficient.
2Device complexity
If a conventional p-type output LDO is used to avoid additional voltage supply, then device complexity is reduced, but power supply ripple rejection ratio deteriorates at mid-range frequencies
Solution Approach 1:
The LDO is segmented into two distinct control loops: a slow loop for DC regulation stability and a fast loop for transient response and PSRR improvement. The fast loop specifically addresses mid-range frequency rejection by providing rapid correction of supply ripple, while the slow loop maintains overall system stability.
Solution Approach 2:
The circuit employs dynamic control with two loops operating at different speeds. The fast loop responds quickly to high-frequency supply variations, while the slow loop handles low-frequency regulation. This dynamic multi-loop approach allows the circuit to adapt its response characteristics across different frequency ranges, improving overall PSRR without sacrificing stability.
3Reliability
If a larger load capacitor is used to improve PSRR at mid-range frequencies in p-type LDO, then power supply ripple rejection ratio is improved, but the size of the LDO increases
Solution Approach 1:
The fast loop provides dynamic compensation for supply ripple at mid-range frequencies, eliminating the need for large static capacitance. By actively correcting high-frequency variations through the fast loop, the circuit achieves good PSRR with minimal capacitor size, reducing both area and power consumption.
Solution Approach 2:
The circuit changes the control strategy from passive capacitance-based filtering to active dynamic control. Instead of relying on large capacitor values to attenuate ripple, the fast loop actively counteracts supply variations, achieving the same PSRR effect with much smaller capacitance values.
Data Source
AI summary
A PMOS-output LDO with full spectrum PSR is disclosed. In one implementation, a LDO includes a pass transistor (MO) having a source coupled to an input voltage (Vin); a noise cancelling transistor (MD) having a source coupled to the Vin, a gate coupled to a drain and a gate of the pass transistor; a source follower transistor (MSF) having a source coupled to a drain of the pass transistor, a drain coupled to the drain and gate of the noise cancelling transistor; a current sink coupled between the drain of the source follower transistor and ground; and an error amplifier having an output to drive the gate of the source follower transistor.