PMOS LDO Regulator Feedback Loop for High-Frequency PSRR
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Solution Overview
Problem
Conventional LDO regulators designed with p-type metal-oxide-semiconductor (PMOS) transistors suffer from limited operational bandwidth and degradation of power supply rejection ratio (PSRR) and reverse PSRR at high frequencies, making them less effective compared to n-type metal-oxide-semiconductor (NMOS) transistors, especially in 5G millimeter-wave frequency synthesizers.
Innovation Solution
A low drop-out (LDO) regulator is implemented using PMOS transistors with a high bandwidth feedback loop, incorporating a first PMOS transistor with its drain coupled to an output node and a second PMOS transistor with its source coupled to the same output node, along with amplifiers to control the gates based on sensed output voltage, enhancing PSRR and RPSRR.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If PMOS transistors are used in LDO regulator, then device complexity is reduced and ease of manufacture is improved, but operational bandwidth is limited and PSRR degradation occurs at high frequencies
Solution Approach 1:
The LDO regulator is segmented into two separate control paths: a first amplifier controls the gate of the PMOS transistor for basic voltage regulation, while a second amplifier controls the gate of the switch transistor for high-frequency PSRR enhancement. This segmentation allows each amplifier to be optimized for its specific function, resolving the contradiction between ease of manufacture and operational bandwidth.
Solution Approach 2:
The switch transistor is dynamically controlled by the second amplifier to enable high-frequency switching that enhances PSRR. The dynamic switching action allows the PMOS-based LDO to achieve high-frequency performance comparable to NMOS implementations, while maintaining the manufacturing advantages of PMOS technology.
2Use of energy by moving object
If conventional PMOS LDO regulator is used, then power consumption is reduced, but PSRR and RPSRR degrade at high frequencies
Solution Approach 1:
A high-frequency feedback path is introduced through the second amplifier and switch transistor. This feedback mechanism senses output voltage variations at high frequencies and rapidly adjusts the switch transistor to compensate, maintaining PSRR performance without significantly increasing power consumption. The feedback operates only when needed for high-frequency correction.
Solution Approach 2:
The invention changes the operating parameters of the PMOS transistor by introducing a controlled switching mechanism. The switch transistor operates in switching mode rather than linear mode, changing its effective resistance characteristics dynamically to maintain low output impedance at high frequencies, thereby improving PSRR while keeping average power consumption low.
3Device complexity
If single amplifier control is used in PMOS LDO, then device complexity is minimized, but bandwidth is limited
Solution Approach 1:
The control function is segmented into two amplifiers with distinct roles: the first amplifier handles low-frequency regulation with high gain, while the second amplifier handles high-frequency stabilization. This segmentation enables bandwidth extension without requiring a single complex high-bandwidth amplifier, thus balancing device complexity and performance.
Solution Approach 2:
The second amplifier serves multiple functions: it provides high-frequency feedback for PSRR enhancement, controls the switch transistor for bandwidth extension, and stabilizes the output at high frequencies. This multi-functionality achieves high bandwidth performance without proportionally increasing device complexity.
Data Source
AI summary
Certain aspects of the present disclosure provide a low drop-out (LDO) regulator. The LDO regulator generally includes a first p-type metal-oxide-semiconductor transistor (PMOS) having a drain coupled to an output node of the LDO regulator, a first amplifier having an input coupled to a reference voltage node and an output coupled to a gate of the first PMOS transistor, a second PMOS transistor having a source coupled to the output node, and a second amplifier having an input coupled to the output node and an output coupled to a gate of the second PMOS transistor.