Power Supply Circuit Leakage Current Suppression
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Solution Overview
Problem
In power supply circuits, the transition from normal to sleep operation leads to an increase in leakage current due to the body diode of PMOS transistors being forward-biased, as the first internal voltage applied to the source and back gate of the transistor decreases, causing a voltage drop that results in increased current consumption.
Innovation Solution
A power supply circuit design where a voltage higher than the sleep voltage is applied to the gate and back gate of the PMOS transistor during sleep operation, ensuring a reverse bias is maintained across the body diode, thereby preventing an increase in leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the power supply circuit switches to sleep operation to reduce power consumption, then current consumption is reduced, but leakage current increases due to forward biasing of the body diode
Solution Approach 1:
The invention applies preliminary anti-action by proactively maintaining reverse bias across the body diode through voltage control before leakage current can increase. Specifically, the control circuit monitors the first internal voltage and adjusts the voltage applied to the gate and back gate of the PMOS transistor to ensure the body diode remains reverse-biased during sleep operation, thereby preventing the forward biasing that would cause increased leakage current.
Solution Approach 2:
The invention applies parameter changes by dynamically adjusting the voltage levels applied to the gate and back gate of the PMOS transistor based on the state of the first internal voltage. During sleep operation, when the first internal voltage decreases, the control circuit increases the voltage on the gate and back gate to maintain reverse bias, effectively changing the electrical parameters to prevent harmful leakage while maintaining low power consumption.
2Use of energy by stationary object
If the first internal voltage is allowed to decrease during sleep operation to save power, then power consumption is reduced, but the body diode becomes forward biased causing increased leakage
Solution Approach 1:
The invention applies feedback by implementing a control circuit that continuously monitors the first internal voltage level and adjusts the gate and back gate voltages accordingly. When the first internal voltage decreases during sleep operation, the feedback mechanism detects this change and responds by adjusting the voltage applied to the PMOS transistor's control terminals to maintain reverse bias on the body diode, thus preventing leakage current while allowing power savings.
3Loss of energy
If a sub LDO unit is used to generate sleep voltage during sleep operation, then power consumption is reduced, but the first internal voltage from the DC/DC converter drops below the sleep voltage causing forward bias
Solution Approach 1:
The invention applies the intermediary principle by introducing a control circuit that acts as a mediator between the sub LDO unit and the PMOS transistor. This control circuit receives the sleep voltage from the sub LDO unit and uses it to adjust the gate and back gate voltages of the PMOS transistor, ensuring reverse bias maintenance. The control circuit serves as an intermediary that reconciles the voltage mismatch between the sub LDO output and the PMOS transistor requirements during sleep operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively suppresses the increase in leakage current during sleep operations by maintaining a reverse bias across the body diode of the PMOS transistor, reducing power consumption and maintaining stable voltage levels.
Implementation Method 1
a PMOS transistor having a source connected to a first internal voltage and configured to output a second internal voltage, which is a voltage of a drain defined by control of a magnitude of a current flowing between the source and the drain
Implementation Method 2
In the transistor TR10, the first internal voltage Vin1 applied to the source and the back gate is lower than the sleep voltage applied to the drain. Thereby, a forward voltage is applied to a body diode (not shown) of the transistor TR10, and as a result, there is a problem in that a leakage current in the transistor TR10 increases.
Data Source
AI summary
A power supply circuit in which an increase in a leakage current can be suppressed is provided. In a power supply circuit in which a main LDO unit outputs a first internal voltage during a normal operation and a sub LDO unit outputs a sleep voltage during a sleep operation, the sleep voltage is applied to a drain of a transistor, and an external voltage higher than the sleep voltage is applied to a gate and a back gate thereof.