PMOS Level Shifter Circuit for Simpler LCD Voltage Conversion
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Solution Overview
Problem
The conventional level shifter circuits in liquid crystal display (LCD) manufacturing require complex processing and multiple masks, leading to increased costs and power loss, necessitating a simplified manufacturing process and reduced power consumption.
Innovation Solution
A level shifter circuit design utilizing a single type of metal oxide semiconductor transistor, comprising specific configurations of transistors, diodes, and capacitors, which simplifies the manufacturing process and reduces power loss by effectively adjusting voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If CMOS field effect transistors are used in the level shifter circuit, then the voltage level shifting function is achieved, but the manufacturing process becomes more complicated and costs increase
Solution Approach 1:
The patent applies homogeneity by using only PMOS transistors (single type) throughout the level shifter circuit, eliminating the need for both NMOS and PMOS devices. This uniform transistor type simplifies the manufacturing process, reduces the number of masks required, and lowers production costs while maintaining the voltage level shifting functionality through proper circuit configuration
2Loss of energy
If CMOS transistors are used in the level shifter circuit, then the voltage level shifting function is achieved, but power loss increases
Solution Approach 1:
The patent changes the operational parameters by using only PMOS transistors with optimized gate control voltages (VGH, VGL, VDD). This parameter optimization reduces unnecessary current flow and power consumption while achieving the required voltage level shifting, thereby reducing power loss compared to conventional CMOS implementations
3Ease of manufacture
If single type PMOS transistors are used, then manufacturing cost is reduced, but the ability to achieve full voltage range may be limited
Solution Approach 1:
The patent employs dynamic gate control using multiple voltage levels (VGH for high, VGL for low, and VDD for supply) applied to the PMOS transistor gates. This dynamic voltage control enables the single-type PMOS circuit to achieve full voltage range output capability, matching the versatility of conventional CMOS circuits while maintaining manufacturing simplicity and cost effectiveness
Data Source
AI summary
A level shifter circuit. It comprises a first level shifter unit which comprises a first transistor, a second transistor, a first diode, a first capacitor, a second diode and a second capacitor. The first transistor comprises a first gate, a first source/drain and a second source/drain. The first source/drain is electrically connected to the first voltage. The second transistor comprises a second gate electrically connected to the second source/drain, a third source/drain and a fourth source/drain respectively electrically connected to the first voltage and the first gate. The first diode has a first end electrically connected to the second source/drain and a second end receiving an inverted clock pulse signal. The first and the second capacitors are respectively electrically connected to the first and the second diodes. The second diode has a first end electrically connected to the fourth source/drain and a second end receiving a clock pulse signal.