PMOS Metal Gate Thickness Optimization for Leakage Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor device fabrication methods face challenges such as leakage current due to tunneling effects and inferior performance caused by boron penetration and depletion effects, especially when using silicon dioxide or silicon oxynitride gate dielectric layers and polysilicon gates, which hinder the progression to next-generation devices.
Innovation Solution
A method for fabricating metal gate CMOS devices with dual work function metal layers, involving the formation of high-k dielectric layers, barrier layers, and specific metal layers on substrates with defined regions, followed by patterning and planarizing processes to create gate structures with distinct metal layers for improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the thickness of the gate dielectric layer is reduced to achieve scaling down, then the device size is reduced, but leakage current increases due to tunneling effect
Solution Approach 1:
The patent changes the dielectric constant parameter of the gate dielectric material from conventional silicon oxide (k≈3.9) to high-k materials (k>20), enabling thicker physical layers while maintaining equivalent oxide thickness and reducing tunneling leakage current
Solution Approach 2:
The patent employs composite gate stack structures combining high-k dielectric layers with metal gate layers, creating a multi-material system that simultaneously achieves low leakage current and high capacitance
2Ease of manufacture
If conventional polysilicon gate is used, then the fabrication process is simple, but performance deteriorates due to boron penetration and depletion effect
Solution Approach 1:
The patent extracts and removes the polysilicon gate material, replacing it entirely with metal gate materials that do not suffer from boron penetration or depletion effects, thereby eliminating the performance deterioration issues
Solution Approach 2:
The patent introduces metal gate materials as an intermediary between the high-k dielectric and the channel, providing superior work function control and eliminating the harmful interactions between polysilicon and dopant atoms
3Ease of manufacture
If uniform metal layer thickness is used in both PMOS and NMOS regions, then the fabrication process is simplified, but performance optimization is limited
Solution Approach 1:
The patent applies different metal layer thicknesses to different device regions: thicker metal layers in PMOS regions and thinner metal layers in NMOS regions, optimizing each region's performance characteristics locally while using selective removal processes to achieve the differentiation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces leakage current and enhances device performance by using high-k dielectric layers and work function metals, achieving superior reliability and capacitance in semiconductor devices.
Implementation Method 1
high-K materials are used to replace the conventional silicon oxide to be the gate dielectric layer because it decreases physical limit thickness effectively, reduces leakage current
Implementation Method 2
work function metals are developed to replace the conventional polysilicon gate to be the control electrode that competent to the high-K gate dielectric layer
Data Source
AI summary
A semiconductor device includes: a substrate having a first region and a second region; a first gate structure disposed on the first region, wherein the first gate structure comprises a first high-k dielectric layer, a first work function metal layer, and a first metal layer disposed between the first high-k dielectric layer and the first work function metal layer; and a second gate structure disposed on the second region, wherein the second gate structure comprises a second high-k dielectric layer, a second work function metal layer, and a second metal layer disposed between the second high-k dielectric layer and the second work function metal layer, wherein the thickness of the second metal layer is lower than the thickness of the first metal layer.