Selective MoSi Deposition on pMOS Without Dual-Silicide Masking
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Solution Overview
Problem
Current dual silicide techniques require complex process flows involving multiple steps to mask and unmask nMOS and pMOS junctions, leading to longer and more complex processes that negatively impact throughput in semiconductor manufacturing.
Innovation Solution
A method for selectively depositing a molybdenum silicide film by exposing a substrate with silicon and silicon germanium materials to a cleaning agent plasma of ammonia and NF3, followed by sequential exposure to a molybdenum precursor and silane precursor, allowing for selective formation of the silicide film on silicon germanium without masking the nMOS junction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple masking and unmasking steps are used to achieve selective silicide deposition, then selectivity between nMOS and pMOS junctions is improved, but process complexity and manufacturing time increase
Solution Approach 1:
The patent changes the chemical parameters of the deposition process by using a plasma-enhanced chemical vapor deposition (PECVD) process with specific precursor gases (silane and germane) and plasma conditions that enable selective silicide formation on pMOS junctions without requiring physical masking. The plasma chemistry and deposition parameters are tuned to achieve selectivity based on material composition rather than geometric masking.
Solution Approach 2:
The patent replaces the mechanical masking system (physical masks and alignment steps) with a chemical selection mechanism. Instead of using opaque masks to block deposition on nMOS regions, the process uses differential chemical reactivity between SiGe source/drain regions and silicon regions in a plasma environment to achieve selective deposition through chemistry rather than mechanics.
2Manufacturing precision
If multiple masking and unmasking steps are used to achieve selective silicide deposition, then selectivity between nMOS and pMOS junctions is improved, but manufacturing throughput decreases
Solution Approach 1:
The patent merges multiple discrete process steps (mask deposition, mask alignment, mask patterning, silicide deposition, mask removal) into a single integrated plasma deposition step. By combining these previously separate operations into one concurrent process using plasma chemistry, the number of cycle steps is reduced and throughput is improved while maintaining selectivity.
Solution Approach 2:
The patent enables continuous processing by eliminating the interruption caused by mask removal steps. The plasma-enhanced deposition process continuously forms the silicide layer selectively on pMOS regions throughout the deposition duration without requiring intermediate mask removal, thereby maintaining continuous productive action and improving manufacturing throughput.
3Manufacturing precision
If masking steps are added to achieve selective deposition, then selectivity is improved, but process time increases
Solution Approach 1:
The patent extracts and removes the masking steps entirely from the process flow. By taking out the mask deposition, alignment, and removal operations, the process time associated with these steps is eliminated. Selectivity is achieved through the intrinsic chemical properties of the materials in the plasma environment rather than through added process steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the dual silicide process flow, reducing the need for masking and unmasking, thereby shortening process times and increasing throughput while maintaining selectivity and achieving desired film thickness and properties.
Implementation Method 1
The cleaning agent comprises a plasma of ammonia and NF3
Implementation Method 2
exposure to the cleaning agent selectively forms a residue on the first material
Implementation Method 3
The substrate surface is exposed to a molybdenum precursor and a reductant to selectively form the molybdenum film on the second material over the first material
Implementation Method 4
The substrate is dechucked by exposing the substrate to an Ar plasma
Data Source
AI summary
Methods for forming a semiconductor structure and semiconductor structures are described. Some embodiments of the method comprise patterning a substrate to form a first opening and a second opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor and the second opening over the p transistor. The substrate is pre-cleaned. A molybdenum film is selectively deposited on the p transistor.