PMOS MTP Flash Memory Programming Method

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Solution Overview

Problem

PMOS MTP flash memory cells fabricated using standard logic CMOS processes face challenges with programming speed and power consumption due to high cell current requirements, especially when using hot carrier injection, which limits multi-bit programming and is inefficient for over-erased cells.

Innovation Solution

A programming method that biases the select gate transistor to a constant drain current level and sweeps the control gate bias voltage from a low to a high voltage level while maintaining the cell current within a predetermined limit, enabling low power and high speed programming using hot carrier injection, and effectively programming over-erased cells.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If hot carrier injection is used for programming PMOS MTP flash memory cells, then programming speed is improved, but power consumption increases due to high cell current requirements

Engineering Contradiction:

Improveprogramming speedVSAvoidpower consumption

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

The patent changes the bias voltage parameters dynamically during programming. It applies a first bias condition with lower voltages to limit cell current and reduce power consumption, then switches to a second bias condition with higher voltages to complete programming. This parameter transformation allows the system to achieve programming speed while controlling power consumption through staged voltage application.

Inventive Principle:

Principle #35Parameter changes

2Speed

If high cell current is applied for programming, then programming speed is improved, but device reliability deteriorates due to excessive current stress

Engineering Contradiction:

Improveprogramming speedVSAvoiddevice reliability

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The patent implements periodic action by applying bias conditions in distinct stages. It first applies a limited bias condition to initiate programming with controlled current, then periodically switches to a second bias condition with higher voltages to complete the programming. This periodic application of different bias conditions allows the cell to be programmed effectively while preventing excessive current stress that would damage the device.

Inventive Principle:

Principle #19Periodic action

3Use of energy by moving object

If bit-by-bit programming is used to reduce power consumption, then power consumption is reduced, but programming speed becomes very slow

Engineering Contradiction:

Improvepower consumptionVSAvoidprogramming speed

Core Design Contradiction:

Use of energy by moving objectVSProductivity

Solution Approach 1:

The patent applies partial action by using the first bias condition with limited voltages to initiate programming and control power consumption, then supplements it with a second bias condition that provides additional programming current. This partial application of high voltage only when needed allows the system to maintain low power consumption during most of the programming process while still achieving adequate programming speed through the supplemental bias condition.

Inventive Principle:

Principle #16Partial or excessive action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method achieves low power consumption while increasing programming speed, allowing for multi-bit programming and reliable programming of over-erased cells, with reduced cell current and the need for a smaller charge pump, resulting in a compact die size and high endurance.

Implementation Method 1

PMOS MTP flash memory cells are programmed using hot carrier injection (HCI). However, when HCI is used for programming, the cell current increases as the programming of the memory cell progresses.

Methodology Applied

Scientific EffectHot carrier injection:

Implementation Method 2

In general, PMOS MTP flash memory cells are programmed using gate induced drain leakage (GIDL).

Methodology Applied

Scientific EffectGate induced drain leakage:

Data Source

PatentUS9672923B1Low power high speed program method for multi-time programmable memory device

Publication Date: 2017.06.06 INTEGRATED SILICON SOLUTION INC

AI summary

A programming method for a PMOS multi-time programmable (MTP) flash memory device biases the select gate transistor to a constant drain current level and sweeps the control gate bias voltage from a low voltage level to a high voltage level while maintaining the cell current around a predetermined cell current limit level. In this manner, the PMOS MTP flash memory device can achieve low power and high speed program using hot carrier injection (HCI). The programming method of the present invention enables multi-bit programming of the PMOS MTP flash memory cells, thereby increasing the programming speed while preserving low power consumption.