PMOS Neural Recording Amplifier for Sub-µV Noise Reduction
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Solution Overview
Problem
Current neural implant systems suffer from high noise levels, particularly in EEG and ENG applications, due to thermal and sparkling noise, which limits their effectiveness and can lead to corrosion and random gain variations, necessitating a solution for sub-µV RMS input noise reduction.
Innovation Solution
A low-noise amplifier design utilizing PMOS input transistors and a fully-differential telescopic architecture with variable power consumption, achieving sub-µV RMS noise levels by optimizing transistor sizes and power management, and incorporating a capacitance multiplier for frequency adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional amplifiers are used in neural implant systems, then the system can detect biopotential signals, but the noise level is high (4 μV RMS or 2 μV RMS) which limits effectiveness for EEG and ENG applications
Solution Approach 1:
The patent changes the transistor type parameter from NMOS to PMOS in the input stage, exploiting the lower flicker noise constant of PMOS transistors (Kp = 20×10^-24 vs Kn = 120×10^-24) to reduce input-referred noise to sub-μV RMS levels while maintaining signal detection capability
Solution Approach 2:
The patent converts the typically harmful flicker noise mechanism into a benefit by carefully selecting PMOS transistors with optimized dimensions and operating points where the 1/f noise characteristic actually helps suppress certain frequency ranges while maintaining overall low noise performance through the lower Kp constant
2Object-affected harmful factors
If BJT-input operational transconductance amplifier is used to reduce noise to 300 nV RMS, then input-referred noise is significantly lower, but residual direct current of 20 nA causes corrosion of contacts and open loop architecture leads to random gain variations
Solution Approach 1:
The patent implements a closed-loop feedback architecture using an operational amplifier with resistive feedback network, which stabilizes the gain against random variations and eliminates the open-loop instability problem while maintaining low noise through the PMOS input stage
Solution Approach 2:
The patent extracts and eliminates the harmful residual DC current component by using the closed-loop feedback configuration with virtual ground at the inverting input, which prevents the 20 nA corrosion-causing current from flowing through the electrode-tissue interface while preserving the low noise amplification function
3Object-affected harmful factors
If chopper amplifier is used to shift signal to higher frequency to eliminate flicker noise, then flicker noise is negligible, but at least ten times more bandwidth is required which increases power consumption
Solution Approach 1:
The patent uses a simple RC low-pass filter with reasonable component values instead of complex chopper modulation circuits, achieving adequate flicker noise suppression through the PMOS transistor's inherently lower Kp constant without requiring excessive bandwidth or consuming additional power for frequency conversion
4Object-affected harmful factors
If variable power consumption is implemented to tune noise from 1.94 to 0.693 μV RMS, then noise performance is optimized for different applications, but device complexity increases
Solution Approach 1:
The patent implements dynamic power management by making the bias current ISS variable, allowing the amplifier to tune its noise performance from 1.94 μV RMS at lower currents to 0.693 μV RMS at higher currents (Iiss = 250 μA), adapting to different application requirements without complex circuit reconfiguration
Data Source
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AI summary
The invention relates to a biocompatible recording system having a number of input channels for acquiring electronic information from the neural system of a living being, comprising a preamplifier and further amplifier stages, wherein an input of a second amplifier stage is coupled to an output of the preamplifier and a low pass filter having a capacitance multiplier is connected to the amplifier of the second stage. The preamplifier of the recording system is designed using P-MOS technology.