P-MOS Power Transistor with N-MOS Bypass for Latch-Up Prevention
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Solution Overview
Problem
Existing IC-based power delivery systems face challenges in efficiently managing power transistors to avoid latch-up conditions and reduce conduction losses, leading to increased size and cost due to the need for boosted voltage generation and thick oxide layers in N-MOS transistors.
Innovation Solution
The use of P-MOS power transistors with N-MOS bypass transistors, coupled directly, and a complementary-MOS gate driver circuit allows for an active-low drive-enable signal, eliminating the need for boosted voltage circuitry and enabling smaller transistor sizes, while safeguards like guard rings and increased spacing reduce the likelihood of latch-up.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If N-MOS power transistors are used in power delivery systems, then conduction losses can be reduced, but the risk of latch-up conditions increases and boosted voltage generation circuitry is required
Solution Approach 1:
The power transistor is segmented into two separate devices: an N-MOS power transistor for conducting high current with low conduction losses, and a P-MOS protection transistor for preventing latch-up conditions. This segmentation allows each transistor to be optimized for its specific function, resolving the contradiction between reducing conduction losses and preventing latch-up.
Solution Approach 2:
The P-MOS protection transistor acts as an intermediary device that monitors and controls the operation of the N-MOS power transistor. It provides a protective function by detecting abnormal conditions and preventing latch-up, while allowing the N-MOS transistor to operate efficiently for power delivery.
2Reliability
If N-MOS power transistors with thick oxide layers are used, then reliability is improved, but device area and cost increase
Solution Approach 1:
The invention changes the operational parameters and structure of the power transistor by using a P-MOS device instead of an N-MOS device for the protection function. This parameter change allows the use of standard-thickness oxide layers while maintaining reliability, thereby reducing the required transistor area and associated costs.
3Power
If boosted voltage generation circuitry is added to N-MOS systems, then power delivery capability is improved, but device complexity and cost increase
Solution Approach 1:
Instead of using N-MOS transistors with boosted voltage generation circuitry to achieve active-low drive capability, the invention inverts the approach by using a P-MOS protection transistor that naturally provides the required drive characteristics. This inversion eliminates the need for complex boosted voltage generation circuitry while maintaining power delivery capability.
Data Source
AI summary
An integrated circuit device for delivering power to a load includes a P-MOS power transistor, an N-MOS bypass transistor and a gate driver circuit. The P-MOS power transistor is coupled between a supply voltage node and a power output node of the integrated circuit device, and the N-MOS bypass transistor is coupled between the power output node and a reference node of the integrated circuit device. The gate driver circuit responds to a pulse-width-modulated (PWM) control signal by outputting an active-low drive-enable signal to a gate terminal of the P-MOS power transistor and an active-high bypass-enable signal to a gate terminal of the N-MOS bypass transistor during respective, non-overlapping intervals.