Dual PMOS NMOS LDO Regulator for Low Dropout and High PSRR

Solution Overview

Problem

Existing linear voltage regulators face challenges in achieving low current consumption, low dropout voltage for digital circuits, and high power supply rejection ratio for analog circuits, while maintaining stability and minimizing noise sensitivity, especially in battery-operated consumer devices.

Innovation Solution

A linear voltage regulator design incorporating a PMOS LDO regulator, a charge pump, and an NMOS LDO regulator, where the PMOS LDO achieves low dropout voltage and the charge pump provides high input voltage for the NMOS LDO to minimize capacitance requirements and maintain feedback loop stability, with a variable resistance transistor and operational amplifier to ensure frequency domain stability and low noise.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If a linear regulator is designed for digital circuits with low ground current and low dropout voltage, then current consumption and voltage drop are reduced, but power supply rejection ratio deteriorates

Engineering Contradiction:

Improveground currentVSAvoidpower supply rejection ratio

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The voltage regulator is divided into two separate regulators: a first linear voltage regulator optimized for digital circuits with low ground current and low dropout voltage, and a second linear voltage regulator optimized for analog circuits with high power supply rejection ratio. Each regulator independently serves its target circuit type, eliminating the need to compromise performance for a single application.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Each voltage regulator is designed with different characteristics tailored to its specific application: the first regulator uses an NMOS power transistor with low threshold voltage for digital circuits, while the second regulator uses a PMOS power transistor with high threshold voltage for analog circuits. This local optimization allows each regulator to excel at its designated function without compromising the other.

Inventive Principle:

Principle #3Local quality

2Reliability

If a linear regulator is designed for analog circuits with high power supply rejection ratio, then noise isolation is improved, but current consumption increases

Engineering Contradiction:

Improvepower supply rejection ratioVSAvoidcurrent consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The voltage regulator is divided into two separate regulators: a first linear voltage regulator optimized for digital circuits with low ground current and low dropout voltage, and a second linear voltage regulator optimized for analog circuits with high power supply rejection ratio. Each regulator independently serves its target circuit type, eliminating the need to compromise performance for a single application.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Each voltage regulator is designed with different characteristics tailored to its specific application: the first regulator uses an NMOS power transistor with low threshold voltage for digital circuits, while the second regulator uses a PMOS power transistor with high threshold voltage for analog circuits. This local optimization allows each regulator to excel at its designated function without compromising the other.

Inventive Principle:

Principle #3Local quality

3Device complexity

If a single voltage regulator serves both digital and analog circuits, then device complexity is reduced, but performance optimization for specific circuits deteriorates

Engineering Contradiction:

Improveregulator structureVSAvoidcircuit-specific performance

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The voltage regulator is divided into two separate regulators: a first linear voltage regulator optimized for digital circuits with low ground current and low dropout voltage, and a second linear voltage regulator optimized for analog circuits with high power supply rejection ratio. Each regulator independently serves its target circuit type, eliminating the need to compromise performance for a single application.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The voltage regulator system provides universal functionality by including both an NMOS-based regulator and a PMOS-based regulator, allowing it to serve both digital and analog circuits with optimized performance for each type. The system adapts to different circuit requirements through the dual-regulator architecture.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS8981739B2Low power low dropout linear voltage regulator

Publication Date: 2015.03.17 NEXTECH SEMICONDUCTOR LLC

AI summary

Embodiments of a linear voltage regulator are described. In one embodiment, the linear voltage regulator includes a PMOS low drop-out (LDO) regulator configured to convert an input voltage to a regulated voltage, a charge pump connected to the PMOS LDO regulator and configured to amplify the regulated voltage into an amplified voltage, and an NMOS LDO regulator connected to the charge pump and configured to convert the amplified voltage into an output voltage. Other embodiments are also described.