Non-volatile Memory Voltage Control via PMOS NMOS Segmentation
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Solution Overview
Problem
Conventional non-volatile semiconductor memory devices face challenges in reducing the voltage required for writing data and in flexibly setting gate voltages for selected memory transistors, leading to increased voltage usage and difficulty in regulating separate gate voltages for selected and non-selected memory cells.
Innovation Solution
The use of PMOS transistors as first semiconductor switches and NMOS transistors as second semiconductor switches allows for separate control of gate voltages in selected and non-selected memory cell column wirings, enabling reduced voltage application and flexible voltage setting for accumulating electric charges in selected memory cell transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If NMOS transistors are used as first semiconductor switches to apply writing prevention voltage to non-selected memory cell transistors, then the gate voltage must be higher than the writing prevention voltage, but this increases the overall voltage requirement and reduces flexibility in voltage setting
Solution Approach 1:
The patent divides the semiconductor switches into two distinct groups: first semiconductor switches (PMOS) for applying writing prevention voltage to non-selected memory cell transistors, and second semiconductor switches (NMOS) for applying writing voltage to selected memory cell transistors. This segmentation allows independent optimization of voltage levels for each function, resolving the contradiction between reliable writing prevention and reduced voltage requirements.
Solution Approach 2:
The patent inverts the conventional approach by using PMOS transistors instead of NMOS transistors as the first semiconductor switches. Since PMOS transistors have opposite polarity characteristics, they can be turned on with a gate voltage lower than the writing prevention voltage applied to their source, thereby reducing the overall voltage requirement while maintaining reliable writing prevention capability.
2Device complexity
If a single gate line is used to control multiple first semiconductor switches, then circuit complexity is reduced, but separate regulation of gate voltages for selected and non-selected memory cells becomes difficult
Solution Approach 1:
The patent segments the gate control system into separate first selected gate lines for controlling first semiconductor switches and second selected gate lines for controlling second semiconductor switches. This segmentation enables independent voltage regulation for selected and non-selected memory cells, achieving both circuit simplicity and voltage regulation flexibility simultaneously.
Solution Approach 2:
The first selected gate lines serve multiple functions: they control the first semiconductor switches to apply writing prevention voltage to non-selected memory cell transistors, and they control the first semiconductor switches in selected memory blocks to enable writing operations. This multi-functionality maintains circuit simplicity while providing voltage regulation flexibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the voltage required for writing data and allows for more flexible voltage settings, lowering the voltage difference between the substrate and gate in switched-on transistors, thereby relaxing electric fields applied to gate insulating films and enhancing the reliability of these films.
Implementation Method 1
a selected memory cell transistor causes a selected memory cell transistor to accumulate electric charges based on a voltage difference between a charge accumulating voltage and a voltage to be applied to word lines
Data Source
AI summary
A non-volatile semiconductor memory device is proposed whereby voltage can be more flexibly set in accumulating electric charges into a selected memory cell transistor in comparison with a conventional device. In a non-volatile semiconductor memory device (1), when a selected memory cell transistor (115) is caused to accumulate electric charges, high voltage as writing prevention voltage is applied from a PMOS transistor (9b) while low voltage as writing voltage is applied from an NMOS transistor (15a). Thus, a role of applying voltage to either the selected memory cell transistor (115) or a non-selected memory cell transistor (116) is shared by the PMOS transistor (9b) and the NMOS transistor (15a). Therefore, the gate voltage and the source voltage of the PMOS transistor (9b) and those of the NMOS transistor (15a) can be separately adjusted, and gate-to-substrate voltage thereof can be finally set to be, for instance, 4[V] or etc.