PMOS-NMOS-PMOS-NMOS NVM Cell Area Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing 4-transistor non-volatile memory (NVM) cells with an all-PMOS structure occupy a large area while maintaining low programming current, necessitating a reduction in cell area without compromising programming efficiency.
Innovation Solution
A 4-transistor NVM cell with a PMOS-NMOS-PMOS-NMOS structure, where NMOS transistors replace PMOS transistors in the control and read positions, allowing for a compact layout by using deep N-wells and isolation techniques, while maintaining the programming method's advantages through reverse Fowler-Nordheim tunneling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If an all-PMOS 4-transistor NVM cell structure is used, then low programming current consumption is achieved, but the cell occupies a relatively large area
Solution Approach 1:
The patent applies local quality by using different transistor types (PMOS and NMOS) in different positions within the same cell structure. Specifically, PMOS transistors are used for the programming transistor while NMOS transistors are used for the read transistor, allowing each transistor type to be optimized for its specific function while achieving both low current consumption and compact area
Solution Approach 2:
The patent employs a composite transistor structure combining PMOS and NMOS devices in a single cell. This composite approach leverages the complementary characteristics of both transistor types - PMOS for low leakage during programming and NMOS for high-speed reading - thereby achieving both low current consumption and reduced cell area
2Area of stationary object
If the cell area is reduced by using compact layout techniques, then integration density is improved, but programming current may increase
Solution Approach 1:
By assigning different transistor types to different functional roles within the compact cell, the patent achieves local optimization where PMOS transistors minimize leakage in the programming path while NMOS transistors provide efficient reading, thereby maintaining low current consumption despite reduced cell area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves a significant reduction in cell area while retaining low programming current consumption and efficient programming sequences, enabling the simultaneous programming of multiple cells without high current power sources.
Implementation Method 1
utilizes reverse Fowler-Nordheim tunneling programming
Data Source
AI summary
A non-volatile memory (NVM) cell structure comprises a PMOS program transistor having source, drain and bulk region electrodes and a gate electrode that is connected to a data storage node; an NMOS control transistor having source, drain and bulk region electrodes that are commonly-connected to receive a control voltage and a gate electrode that is connected to the data storage node; a PMOS erase transistor having source, drain and bulk region electrodes that are commonly-connected to receive an erase voltage and a gate electrode that is connected to the data storage node; and an NMOS read transistor having source, drain and bulk region electrodes and a gate electrode connected to the data storage node.