Dynamic PMOS Gate Overdrive for High-Frequency I/O Level Shifters
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Solution Overview
Problem
Existing input/output (I/O) drivers require multiple power supplies to generate sufficient gate voltages for high-frequency operation, leading to increased IC footprint and potential insufficient voltage for proper transistor operation, which can affect performance and efficiency.
Innovation Solution
The implementation of a dynamic or temporary gate overdrive circuit that reduces the gate drive voltage for PMOS FETs during specific transitions of the output voltage signal, allowing for effective operation with fewer power supplies and maintaining transistor reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple power supplies are used to generate sufficient gate voltages for high-frequency operation, then transistor performance is improved, but IC footprint increases
Solution Approach 1:
The patent dynamically changes the gate voltage parameter by applying overdrive voltages only during specific transition periods (rising and falling edges) rather than maintaining high voltages continuously. This temporary parameter enhancement allows smaller transistors to achieve the necessary drive strength for high-frequency operation without requiring multiple power supplies, thereby reducing IC footprint while maintaining performance
Solution Approach 2:
The patent implements dynamic gate voltage control where the gate voltage is temporarily enhanced during transitions and reduced during steady states. This dynamic approach allows the transistor to operate effectively at high frequencies with smaller dimensions, eliminating the need for multiple power supplies and reducing the overall IC footprint
2Speed
If transistor size is reduced for high-frequency operation and small footprint, then frequency performance is improved, but gate voltage sufficiency deteriorates
Solution Approach 1:
The patent applies gate overdrive voltages in advance during the transition periods before the actual switching action. This preliminary voltage enhancement ensures that smaller transistors have sufficient drive capability to switch quickly and reliably, maintaining both high-frequency performance and voltage sufficiency without requiring larger device dimensions
Solution Approach 2:
The patent employs periodic application of overdrive voltages synchronized with the switching transitions. By applying enhanced gate voltages only during the necessary transition windows (rising and falling edges) and reducing them during steady states, the patent ensures smaller transistors achieve sufficient drive strength for reliable high-frequency operation while minimizing power consumption
Data Source
AI summary
An apparatus for generating an output voltage signal based on an input voltage signal. The apparatus includes a first field effect transistor (FET) including a first gate configured to receive a first gate voltage based on the input voltage signal; a second (FET) including a second gate configured to receive a second gate voltage based on the input voltage signal, wherein the first and second FETs are coupled in series between a first voltage rail and a second voltage rail, and wherein the output voltage signal is produced at an output node between the first and second FETs; and a gate overdrive circuit configured to temporarily reduce the first gate voltage during a portion of a transition of the output voltage signal from a logic low level to a logic high level.