SiGe Abnormal Growth Prevention on PMOS Poly Gates
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Solution Overview
Problem
Conventional methods for forming strained-channel PMOS transistors are susceptible to the formation of SiGe abnormal growths on polycrystalline gate electrodes, leading to degraded device yield due to exposure of the side wall region during the epitaxial growth of SiGe source and drain regions.
Innovation Solution
A method involving plasma nitridation to convert the surface of a polycrystalline layer to silicon nitride, forming a protective layer and an inorganic anti-reflective coating (IARC) layer, and etching to create a stacked structure with a silicon nitride cap that covers the poly gate electrode, preventing SiGe abnormal growths during the formation of SiGe source and drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional methods are used to form SiGe source and drain regions through epitaxial growth, then the strained-channel PMOS transistor structure is achieved, but SiGe abnormal growths form on the poly-Si gate electrodes, degrading device yield
Solution Approach 1:
The patent applies preliminary action by forming a protective layer of silicon nitride on the poly-Si gate electrode surface before the epitaxial growth of SiGe source and drain regions. This protective layer is formed through plasma nitridation treatment, which converts the surface of the poly-Si gate electrode to silicon nitride. By performing this protective action beforehand, the patent prevents SiGe abnormal growths from forming on the gate electrode during subsequent epitaxial processing, thereby resolving the technical contradiction between achieving the strained-channel structure and preventing harmful SiGe growths that degrade device yield
Solution Approach 2:
The patent employs an intermediary approach by introducing a silicon nitride protective layer as a mediator between the poly-Si gate electrode and the SiGe source/drain regions. This intermediate layer acts as a barrier that prevents direct interaction between the SiGe material and the gate electrode surface during epitaxial growth, thereby preventing abnormal SiGe growths while allowing the strained-channel PMOS transistor structure to be formed. The protective layer is subsequently removed after serving its protective function, having successfully prevented the harmful effects
2Object-generated harmful factors
If the side wall region is exposed during epitaxial growth, then SiGe abnormal growths occur on the gate electrode, but additional protective structures increase process complexity
Solution Approach 1:
The patent applies preliminary action by performing plasma nitridation treatment on the poly-Si gate electrode surface before forming the SiGe source and drain regions. This preliminary protective action converts the surface to silicon nitride, which prevents SiGe abnormal growths during epitaxial processing. By addressing the protection need beforehand rather than adding complex side wall structures, the patent reduces overall process complexity while effectively preventing the harmful SiGe growths
Solution Approach 2:
The patent applies parameter changes by modifying the surface chemical composition of the poly-Si gate electrode through plasma nitridation. This treatment changes the surface parameters from pure silicon to silicon nitride, fundamentally altering the surface properties to prevent SiGe abnormal growths. This parameter change approach is simpler than adding structural elements and effectively prevents the harmful effects without increasing device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method significantly reduces the formation of SiGe abnormal growths on polycrystalline gate electrodes, enhancing the yield of strained-channel PMOS transistors by protecting the gate electrode and allowing for low-temperature deposition of protective layers.
Implementation Method 1
A method involving plasma nitridation to convert the surface of a polycrystalline layer to silicon nitride
Data Source
AI summary
The likelihood of forming silicon germanium abnormal growths, which can be undesirably formed on the gate electrode of a strained-channel PMOS transistor at the same time that silicon germanium source and drain regions are formed, is substantially reduced by using protection materials that reduce the likelihood that the gate electrode is exposed during the formation of the silicon germanium source and drain regions.