PMOS Read-Assist Circuit for SRAM Temperature Compensation
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Solution Overview
Problem
Conventional read-assist circuits for SRAM arrays fail to provide adequate temperature compensation, leading to performance penalties at lower operating temperatures and process mismatches between SRAM and periphery logic corners, which affects signal noise margin and writeability.
Innovation Solution
A read-assist circuit utilizing exclusively PMOS transistors with a temperature compensation circuit that generates wordline lowering inversely proportional to operating temperature, independent of process variations, ensuring robustness and minimizing the need for post-fabrication tuning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional read-assist circuits are used, then wordline lowering is achieved, but temperature compensation is insufficient leading to performance penalties at lower operating temperatures
Solution Approach 1:
The patent implements dynamic wordline lowering by using a temperature-dependent biasing scheme where the wordline voltage is adjusted based on operating temperature. A temperature sensing circuit generates a bias voltage that varies with temperature, causing the wordline lowering amount to be dynamically adapted - larger lowering at high temperatures for stability, minimal lowering at low temperatures to maintain performance.
Solution Approach 2:
The patent changes the electrical parameter (wordline voltage) based on temperature conditions. By using a temperature-dependent biasing circuit, the wordline voltage parameter is automatically adjusted according to operating temperature, achieving optimal read stability across different temperature ranges without requiring separate circuit designs for each temperature condition.
2Manufacturing precision
If process variations occur in nanometer scale fabrication, then NMOS pull-up transistors become stronger than PMOS pull-down transistors, but signal noise margin degrades
Solution Approach 1:
The patent implements feedback by using a temperature sensing circuit that monitors operating conditions and automatically adjusts the wordline bias voltage accordingly. The feedback mechanism compensates for process variations and temperature effects on transistor characteristics, maintaining optimal signal noise margin without requiring manual tuning or over-designing the transistors during fabrication.
Data Source
AI summary
PMOS-based temperature compensated read-assist circuits for low-Vmin 6T SRAM bitcells realized in nanometer scale (e.g., 7 nm) CMOS FinFET technologies generate maximum wordline lowering (lower wordline voltages) at higher temperatures and minimum wordline lowering (higher wordline voltages) at lower operating temperatures in way that is substantially process independent and avoids post-silicon tuning. A read-assist PMOS transistor is connected between an associated wordline and VSS and controlled by a temperature compensation signal produced at an intermediate node between weak pull-up and strong pull-down PMOS transistors that are connected in series between VDD and VSS and respectively controlled by VDD and VSS during read operations. This configuration generates the temperature compensation signal at a level closer to VSS at high temperatures than at low temperatures, whereby write-ability is not impacted by the read-assist circuit at low temperature. An optional actuation circuit disables the temperature compensation circuit during non-active cycles to prevent current leakage.