PMOS Scan Driver Circuit for Low-Leakage Pixel Driving
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Solution Overview
Problem
Scan drivers using NMOS transistors in display devices experience leakage currents, leading to operational failures due to the normal functioning of the scan driver.
Innovation Solution
A scan driver design utilizing PMOS transistors, incorporating stages with logic circuits, output circuits, and concurrent driving circuits to control node voltages, enabling the generation of scan signals that effectively turn on NMOS transistors of pixels, while minimizing leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If NMOS transistors are used in the scan driver to generate active high scan signals, then the scan driver can turn on the NMOS transistors of the pixels, but leakage currents occur through the NMOS transistors causing operational failures
Solution Approach 1:
The patent inverts the conventional approach by using PMOS transistors instead of NMOS transistors in the scan driver. PMOS transistors generate active low scan signals instead of active high signals, which eliminates the leakage current problem that occurs with NMOS transistors. This inversion of the transistor type and signal polarity resolves the contradiction between being able to turn on pixel transistors and avoiding leakage currents.
2Object-generated harmful factors
If PMOS transistors are used in the scan driver, then leakage currents are minimized, but the scan driver must generate active low scan signals instead of active high signals
Solution Approach 1:
The patent changes the voltage level parameters of the scan signals from active high to active low. By inverting the logic levels and using complementary clock signals, the PMOS-based scan driver generates active low scan signals that are compatible with the display panel's pixel transistors. This parameter change allows the system to maintain functionality while eliminating leakage currents.
Data Source
AI summary
A scan driver including stages, at least one stage including a logic circuit configured to control a voltage of a first node and a voltage of a second node based on an input signal, a first clock signal, and a second clock signal in a progressive driving period, an output circuit configured to receive the first clock signal and a concurrent driving signal, and to output a scan signal in response to the voltage of the first node and the voltage of the second node, and a concurrent driving circuit configured to control the voltage of the first node and the voltage of the second node in response to an inverted concurrent driving signal in a concurrent driving period such that the output circuit is configured to output the concurrent driving signal as the scan signal in the concurrent driving period.