PMOS-Only Scan Driver Logic for On-Panel OLED Integration
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Solution Overview
Problem
Conventional scan drivers for OLED displays require both PMOS and NMOS transistors, increasing the number of production steps and manufacturing costs due to the need for multiple masks, making it challenging to integrate them directly onto the display panel.
Innovation Solution
A logic gate and scan driver design utilizing only PMOS transistors, specifically an OR gate circuit with multiple drivers and transistors of the same polarity type, allowing for integration onto the OLED display panel without increasing production steps or costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional scan driver composed of PMOS and NMOS transistors is used, then the scan driver can be formed on the panel, but the number of masks and production steps will increase
Solution Approach 1:
The patent applies homogeneity by designing the scan driver circuit to use only PMOS transistors (single polarity type) instead of mixing PMOS and NMOS transistors. This is achieved through careful circuit design where all switching elements are PMOS transistors, and the logic gates (AND, OR, NOT) are implemented using only PMOS transistors with appropriate voltage level management. This homogeneous approach reduces the number of masks and production steps required for manufacturing.
2Ease of manufacture
If scan driver is integrated onto the panel, then manufacturing cost is reduced, but it requires MOS transistors of single polarity type only
Solution Approach 1:
The patent employs parameter changes by operating the entire scan driver circuit at voltage levels and conditions suitable for PMOS transistors only. The circuit design includes voltage level shifting and logic gate implementations that are specifically optimized for PMOS operation, allowing the scan driver to be integrated onto the panel using only PMOS transistors, thereby reducing manufacturing cost while meeting the single polarity type constraint.
3Ease of manufacture
If logic gates are designed with single polarity MOS transistors, then integration onto panel is enabled, but circuit design complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the scan driver into modular logic gate units (AND gates, OR gates, NOT gates), where each gate is independently designed using only PMOS transistors. This modular approach allows each logic gate to be optimized separately for PMOS implementation, making the overall circuit design more manageable and enabling integration onto the panel despite the single polarity constraint.
Solution Approach 2:
The patent uses intermediary elements such as voltage level shifters and intermediate nodes to facilitate PMOS-only logic gate design. These intermediaries help manage the voltage levels and signal transitions required for PMOS operation, enabling complex logic functions to be implemented using only PMOS transistors while maintaining integration capability onto the panel.
Data Source
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AI summary
Disclosed is a logic gate and a scan driver capable of being realized with MOS transistors of a single polarity type only, preferably PMOS transistors. The logic gate comprises a plurality of input terminals (IN1-IN3), a first driver (10), a second driver (12), a third driver (14), a control transistors (M8), a first capacitor (C2), and a fourth driver (16). The first driver (12) is adapted to provide a first power supply voltage (VDD) to a first node (N1) corresponding to a logic combination of the plurality of input signals and the second driver (14) is adapted to provide a second power supply voltage (VSS) to the first node (N1) when the first driver (12) does not provide the first power supply voltage (VDD) to the first node (N1). The third driver (14) is adapted to provide the first power supply voltage (VDD) to an output terminal of the logic gate when the second power supply voltage (VSS) is provided to the first node (N1) and the fourth driver (16) is adapted to provide the second power supply voltage (VSS) to the gate electrode of the control transistor (M8) when the third driver (14) does not provide the first power supply voltage (VDD) to the output terminal. Each of the first driver (10), the second driver (12), the third driver (14), and the fourth driver (16) comprises at least one transistor. These transistors and the control transistor are MOS transistors of the same polarity type.