Two-Phase PMOS Shift Register for Lower-Power Large Panels
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional shift register circuits for organic electroluminescent displays require a large number of thin-film transistors, leading to high power consumption and difficulty in mounting on large-sized panels, while also facing challenges in reducing the size, weight, and production cost.
Innovation Solution
A 2-phase shift register circuit utilizing PMOS transistors and capacitors, with specific switching devices and clock signal phases to reduce the number of transistors and power consumption, and enhance production yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If conventional shift register circuits using PMOS and NMOS transistors are used, then the circuit can operate with wide frequency band and low power consumption, but the number of transistors increases and mounting on large panels becomes difficult
Solution Approach 1:
The patent extracts and removes the NMOS transistor from the conventional CMOS shift register circuit, retaining only the PMOS transistor. This extraction reduces the transistor count from two per stage to one per stage, thereby reducing device complexity and facilitating mounting on large panels while maintaining the low power consumption characteristic
Solution Approach 2:
The patent changes the circuit configuration parameters by introducing specific capacitor connections and clock signal phase relationships. The capacitors are connected to hold gate voltages, and two-phase clock signals are used to control the PMOS transistors in a sequential manner, enabling the circuit to maintain proper operation with reduced transistor count
2Ease of manufacture
If the number of TFTs is decreased to reduce production cost, then manufacturing cost is reduced, but circuit reliability may be deteriorated
Solution Approach 1:
The patent implements beforehand cushioning by using capacitors to pre-hold the gate voltages of PMOS transistors. This ensures that the transistors maintain their required voltage states throughout the clock cycle, preventing reliability issues that might arise from voltage fluctuations or insufficient drive strength with reduced transistor count
Solution Approach 2:
The patent introduces capacitors as intermediary elements that mediate between the clock signals and the PMOS transistor gates. These capacitors store and release charge to maintain proper voltage levels, ensuring reliable circuit operation despite the reduced number of transistors
3Area of stationary object
If conventional shift register is mounted on large-sized panel, then display size is increased, but the size and weight of the panel increase
Solution Approach 1:
By extracting and removing unnecessary NMOS transistors from each shift register stage, the patent reduces the overall transistor count in the scan driver circuit. This reduction directly decreases the circuit area and weight, enabling large-panel displays without proportionally increasing weight
Solution Approach 2:
The patent optimizes the spatial arrangement of remaining PMOS transistors and capacitors in a compact configuration. By carefully designing the layout in the available planar space, the circuit achieves high integration density, allowing the scan driver to be mounted on large panels without significantly increasing overall panel weight
Data Source
AI summary
A shift register circuit comprising a plurality of stages dependently connected to an initial input signal or an output signal of a previous stage and connected to first and second clock signals which are mutually inverted. Each stage includes eight switching devices interconnected together with three capacitors and interfaced through eleven interface points. Some of the interface points are connected to the first and second clock signals according to whether the stage is an even numbered stage or an odd numbered stage. Other ones of the interface points are connectable to the first and second clock signals in alternative ways to reduce power consumption without changing an internal configuration of the stage.