PMOS SiGe-last Integration for Stress Retention
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Solution Overview
Problem
The formation of SiGe source/drain regions in PMOS transistors within CMOS integrated circuits often results in reduced stress in channel regions due to relaxation during thermal anneals, and forming these regions before anneals can deactivate dopants, posing challenges in achieving optimal transistor performance.
Innovation Solution
A process involving a dual layer hard mask to block SiGe growth on PMOS gates, followed by a stress memorization technique, where SiGe source/drain regions are formed after anneals, ensuring higher stress in PMOS channel regions and maintaining dopant activation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stress or pressure
If SiGe source/drain regions are formed prior to thermal anneals, then compressive stress is added to PMOS channel regions, but stress relaxation occurs during anneals reducing the stress benefit
Solution Approach 1:
The patent applies preliminary action by forming the SiGe source/drain regions after the thermal anneals rather than before. This reverses the conventional sequence to avoid stress relaxation during annealing, thereby preserving the compressive stress in the PMOS channel regions throughout the thermal processing steps.
Solution Approach 2:
The patent changes the temporal parameter of the process sequence by delaying SiGe formation until after annealing is complete. This parameter change ensures that the stress-inducing material is introduced only when thermal processing is finished, preventing any stress relaxation that would occur if SiGe were present during high-temperature anneals.
2Stability of the object's composition
If SiGe source/drain regions are formed after thermal anneals, then stress relaxation is avoided, but dopant activation is lost
Solution Approach 1:
The patent segments the source/drain formation into two distinct parts: first forming the doped source/drain regions through ion implantation and annealing, then separately forming the SiGe stress-inducing regions after annealing. This segmentation allows dopant activation to occur during the anneal while stress is added afterward, resolving the contradiction between stress stability and dopant activation.
Solution Approach 2:
The patent performs dopant activation through thermal annealing as a preliminary action before forming the SiGe source/drain regions. This ensures that dopants are properly activated and electrically functional before the stress-inducing SiGe material is introduced, maintaining both dopant reliability and stress stability.
3Ease of manufacture
If a single layer hard mask is used, then the process is simpler, but SiGe growth cannot be blocked on polysilicon gates
Solution Approach 1:
The patent segments the hard mask into two distinct layers: a first hard mask layer for defining source/drain regions and a second hard mask layer for blocking SiGe growth on polysilicon gates. This segmentation enables selective SiGe formation only in desired regions while maintaining a relatively simple dual-layer structure that adds minimal process complexity.
Solution Approach 2:
The patent introduces a second hard mask layer as an intermediary specifically designed to block SiGe growth on polysilicon gates. This intermediary layer acts as a selective barrier that prevents unwanted SiGe formation on gates while allowing SiGe growth in source/drain regions, achieving manufacturing precision with minimal added complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach maintains higher stress in PMOS channel regions and activates dopants, improving transistor performance by avoiding stress relaxation and dopant deactivation issues present in other CMOS integration schemes.
Implementation Method 1
subsequent SiGe epitaxial growth in PSD regions. The bottom hard mask layer blocks SiGe growth on the polysilicon PMOS gate
Implementation Method 2
P-channel metal oxide semiconductor (PMOS) transistors may benefit from compressive stress in channel regions. Silicon-germanium (SiGe) epitaxial material may be grown in source/drain regions of PMOS transistors to add compressive stress
Data Source
AI summary
A process of forming a CMOS integrated circuit including integrating SiGe source/drains in the PMOS transistor after source/drain and LDD implants and anneals. A dual layer hard mask is formed on a polysilicon gate layer. The bottom layer prevents SiGe growth on the polysilicon gate. The top layer protects the bottom layer during source/drain spacer removal. A stress memorization layer may be formed on the integrated circuit prior to a source/drain anneal and removed prior to forming a SiGe blocking layer over the NMOS. SiGe spacers may be formed on the PMOS gate to laterally offset the SiGe recesses.