Recess Etch for Epitaxial SiGe in PMOS Transistors
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Solution Overview
Problem
Conventional recess etch processes for epitaxial SiGe in PMOS transistors often fail to achieve optimal channel stress and mobility enhancement, leading to subpar transistor performance due to limitations in shaping and placement of epitaxial SiGe regions.
Innovation Solution
A combination of ex-situ and in-situ recess etch processes is used to form funnel-shaped or isosceles trapezoid-shaped epitaxial SiGe regions, with the ex-situ etch creating perpendicular recesses and the in-situ etch undercutting the epi sidewalls to facilitate precise placement of SiGe close to the channel, enhancing mechanical stress and mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional recess etch processes are used, then the etching process is simple and fast, but the epitaxial SiGe regions cannot achieve optimal channel stress and mobility enhancement
Solution Approach 1:
The recess etch process is divided into two distinct stages: ex-situ etching to create perpendicular recesses, and in-situ etching to form funnel-shaped or isosceles trapezoid-shaped epitaxial SiGe regions. This segmentation allows each etching step to be optimized for its specific function, achieving precise channel stress control while maintaining process manageability
Solution Approach 2:
The ex-situ etching is performed first to create perpendicular recesses that define the basic geometry and depth. This preliminary action establishes a controlled foundation that enables the subsequent in-situ etching to precisely form the final funnel-shaped or isosceles trapezoid-shaped epitaxial SiGe regions with optimal channel stress characteristics
2Reliability
If epitaxial SiGe regions are placed close to the channel to enhance mobility, then hole mobility and drive current increase, but the placement precision requirements become more stringent
Solution Approach 1:
The dual etching approach creates locally optimized geometries: perpendicular recesses from ex-situ etching provide uniform depth control, while the subsequent in-situ etching forms funnel-shaped or isosceles trapezoid-shaped regions that concentrate mechanical stress precisely where needed near the channel, achieving both high mobility and placement precision
Solution Approach 2:
The process utilizes controlled changes in etching parameters between ex-situ and in-situ steps, including etching chemistry, temperature, and power settings, to transform the recess geometry from perpendicular to funnel-shaped or isosceles trapezoid-shaped, enabling precise control of epitaxial SiGe placement and channel stress distribution
Data Source
AI summary
A PMOS transistor and a method for fabricating a PMOS transistor. The method may include providing a semiconductor wafer having a PMOS transistor gate stack, source/drain extension regions, and active regions. The method may also include forming epi sidewalls, performing a ex-situ recess etch, and performing an in-situ recess etch. The ex-situ recess etch and the in-situ recess etch form recessed active regions. The PMOS transistor is formed by a method using ex-situ and in-situ etch and has epitaxial SiGe regions with a greatest width at the surface of the semiconductor wafer.