PMOS Step-Down Voltage Circuit with Reverse Current Block
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Solution Overview
Problem
Conventional step-down converter circuits face instability and reverse current issues when the input voltage is lower than the output voltage, leading to potential discharge of accumulated charge in lithium secondary batteries, especially in energy harvesting applications where voltage fluctuations are common.
Innovation Solution
A circuit configuration that includes a PMOS transistor with a control circuit and comparator, which connects the input or output node to an internal voltage line based on voltage drop conditions, and a block circuit to prevent reverse-flow paths, ensuring stable operation and preventing current flow back to the input.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional step-down converter circuit is used, then voltage regulation from high input voltage to low output voltage is achieved, but the circuit becomes unstable and allows reverse current flow when input voltage drops below output voltage
Solution Approach 1:
The patent implements dynamic switching between two operational modes based on voltage conditions. When VIN > VOUT, the circuit operates as a conventional step-down converter. When VIN < VOUT, the circuit automatically switches to a different configuration where the PMOS transistor blocks reverse current and the output voltage is fed back to the input node, allowing the circuit to adapt to varying voltage conditions and maintain stability across a wider voltage range
Solution Approach 2:
The patent changes the operational parameters of the PMOS transistor based on voltage conditions. By monitoring the voltage difference between input and output, the control circuit adjusts the gate voltage of the PMOS transistor to either enable normal step-down operation or switch to reverse-current-blocking mode, thereby maintaining circuit reliability across different voltage scenarios
2Adaptability or versatility
If the input voltage is allowed to drop below output voltage, then energy harvesting flexibility is improved, but reverse current discharges the battery and reduces efficiency
Solution Approach 1:
The patent converts the potentially harmful reverse current flow into a beneficial feature. When VIN < VOUT, instead of allowing destructive reverse current to discharge the battery, the circuit automatically switches configuration to block the reverse current path. The output voltage is fed back to the input node through the PMOS transistor, effectively preventing energy loss while still allowing the circuit to operate with fluctuating input voltages from energy harvesters
3Loss of energy
If reverse current protection is added to prevent battery discharge, then energy loss is reduced, but circuit complexity increases
Solution Approach 1:
The patent makes the existing PMOS transistor serve multiple functions: during normal operation (VIN > VOUT), it acts as the main power switch for voltage step-down; during reverse voltage conditions (VIN < VOUT), it automatically switches to block reverse current and transfer output voltage back to the input node. This multi-functionality eliminates the need for separate protection circuits, reducing overall circuit complexity while providing comprehensive reverse current protection
Solution Approach 2:
The patent merges the reverse current protection function with the existing voltage regulation function by using the same PMOS transistor and control circuitry for both purposes. The control circuit integrates voltage comparison and transistor gating functions, combining what could have been separate protection and regulation systems into a unified circuit that achieves both voltage regulation and reverse current prevention
Data Source
AI summary
A circuit includes a PMOS transistor having a source coupled to an input node and a drain coupled to an output node, a control circuit operating with a voltage of an internal line to control a gate voltage of the PMOS transistor, a comparator operating with the voltage of the internal line to cause a comparator output to change from a first state to a second state in response to a drop of voltage of the input node, a switch circuit configured to connect the input node to the internal line when the comparator output is in the first state, and to connect the output node to the internal line when the comparator output is in the second state, and a block circuit configured to block a path from the output node to the input node through the PMOS transistor when the comparator output is in the second state.