PMOS Gate Structure with Tapered Source/Drain Stress Layer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor manufacturing techniques face challenges in improving the carrier mobility of PMOS transistors, particularly due to issues with stress control in the channel region and the subsequent impact on drive current and electrical performance.
Innovation Solution
A method for fabricating a semiconductor structure involves forming a bulk layer with a substantially flat reshaped surface in the source/drain openings, followed by the deposition of a protective layer. This approach ensures uniform thickness and enhanced protective ability, thereby maintaining the bulk layer's volume and stress, which are critical for improving carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the source/drain opening is formed with a conventional shape, then the fabrication process is simple, but the protective layer cannot achieve uniform thickness and the bulk layer volume is reduced
Solution Approach 1:
The source/drain opening is designed with a tapered shape where the width at the bottom is smaller than the width at the top, creating curved sidewalls with apex angles between 45-90 degrees. This curvature allows the protective layer to deposit uniformly across the bulk layer surface while maintaining adequate bulk layer volume, resolving the contradiction between thickness uniformity and structural complexity.
2Ease of manufacture
If the bulk layer volume is reduced to simplify fabrication, then the manufacturing process is easier, but the stress in the bulk layer decreases and carrier mobility cannot be improved
Solution Approach 1:
The patent optimizes the tapered opening geometry by controlling apex angles (45-90 degrees) and width ratios (bottom width 0.5-0.8 times top width) to maintain adequate bulk layer volume. Additionally, the bulk layer composition is adjusted with 10-50% germanium content to enhance stress effects, allowing smaller volumes to achieve the same carrier mobility improvement while simplifying fabrication.
3Reliability
If the protective layer is made thicker to improve protection, then the protective ability increases, but the fabrication process becomes more complex and time-consuming
Solution Approach 1:
The bulk layer is formed with an optimized tapered configuration before depositing the protective layer, creating a geometry that naturally supports uniform thin protective layer deposition. This preliminary structural preparation allows achieving adequate protection with thinner layers (5-20 nm), reducing deposition time and process complexity while maintaining protective effectiveness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed method effectively increases the carrier mobility of the channel region by maintaining a substantial volume and stress in the bulk layer, thereby enhancing the electrical performance of PMOS transistors without compromising the complexity of the fabrication process.
Implementation Method 1
Silicon germanium is used to introduce a compressive stress formed by the lattice mismatch between silicon and silicon germanium to control the carrier mobility.
Data Source
AI summary
Semiconductor structures is provided. The semiconductor structure includes a semiconductor substrate having a first region and a second region. A surface of the first region of the semiconductor substrate contains a gate structure, a surface of the second region of the semiconductor substrate contains a dummy gate structure, and the semiconductor substrate under the dummy gate structure contains an isolation structure. The semiconductor structure further includes a bulk layer having a substantially flat reshaped surface formed in the semiconductor substrate at each of two sides of the gate structure; and a protective layer formed on the reshaped surface of the bulk layer.