PMOS Thin-Film Transistor Electrical Aging for Leakage Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
PMOS thin film transistors in display panels, particularly in AMOLED displays, suffer from high leakage current, which affects performance and is difficult to reduce without increasing transistor size or altering structural design.
Innovation Solution
Applying specific voltage amplitudes to the gate, source, and drain of PMOS thin film transistors for a predetermined time, with Vd-Vs < 0, to electrically age the transistors, reducing leakage current without changing the transistor or circuit design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If the channel width of the TFT is reduced to decrease leakage current, then the leakage current is reduced, but the transistor size cannot be reduced further due to silicon crystal limitations
Solution Approach 1:
The patent applies parameter changes by introducing specific voltage conditions (Vgs > 0V and Vds < -5V) to induce electrical aging effects in the PMOS TFT. This changes the electrical parameters of the transistor over time, reducing leakage current without modifying the physical structure or dimensions of the device, thereby maintaining design flexibility while achieving the desired reduction in harmful leakage current.
2Object-generated harmful factors
If the channel length of the TFT is increased to decrease leakage current, then the leakage current is reduced, but the transistor size increases
Solution Approach 1:
The patent uses parameter changes by applying specific voltage stress conditions (Vgs > 0V and Vds < -5V) to electrically age the PMOS TFT, thereby reducing leakage current without increasing the physical dimensions of the transistor. This allows the channel length to remain small while still achieving leakage reduction through electrical parameter modification rather than geometric scaling.
3Object-generated harmful factors
If the dual-gate TFT structure is employed to decrease leakage current, then the leakage current is reduced, but the transistor size and device complexity increase
Solution Approach 1:
The patent applies parameter changes by introducing specific voltage stress conditions (Vgs > 0V and Vds < -5V) to induce electrical aging in the PMOS TFT. This electrical aging process modifies the electrical parameters of the transistor to reduce leakage current without requiring any structural modifications such as dual-gate configurations, thereby maintaining simple device architecture while achieving the desired leakage reduction.
4Object-generated harmful factors
If electrical aging is applied to reduce leakage current, then the leakage current is reduced, but additional processing time is required
Solution Approach 1:
The patent applies periodic action by using pulsed voltage signals instead of continuous DC voltage for electrical aging. The method employs pulse widths of 1ms to 10s with duty cycles of 1% to 100%, allowing the transistor to be aged under controlled periodic stress conditions. This periodic application of voltage stress reduces the total aging time compared to continuous DC stress while still achieving effective leakage current reduction.
Solution Approach 2:
The patent applies dynamics by making the voltage stress conditions adjustable and adaptable. The gate-source voltage Vgs can be set between 0.1V to 10V and drain-source voltage Vds between -5V to -20V, with pulse widths and duty cycles that can be optimized based on specific application requirements. This dynamic parameter adjustment allows the aging process to be optimized for different transistor types and application scenarios, reducing unnecessary processing time.
Data Source
AI summary
The present disclosure relates to a method of electrically aging a PMOS thin film transistor. The method includes applying a first voltage Vg with an amplitude of A volts to a gate of the PMOS thin film transistor; applying a second voltage Vs with an amplitude of (A−40) to (A−8) volts to a source of the PMOS thin film transistor; and applying a third voltage Vd with an amplitude of (A−80) to (A−16) volts to a drain of the PMOS thin film transistor. Application of the first voltage Vg, the second voltage Vs and the third voltage Vd is maintained for a predetermined time period, and Vd−Vs<0. In this way, reduction of a leakage current of the PMOS thin film transistor is achieved without changing a structural design of the thin film transistor.