PMOS Thin-Film Transistor Electrical Aging for Leakage Reduction
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Solution Overview
Problem
The leakage current in PMOS thin film transistors, particularly in AMOLED display panels, poses performance issues such as bright spots and light leakage, and existing methods to reduce it either require structural changes to the transistors or circuits, which are not adaptable to complex pixel circuits.
Innovation Solution
A method of electrically aging PMOS thin film transistors by applying specific voltage amplitude conditions, including a gate voltage, source voltage, and drain voltage, for a predetermined time period to reduce leakage currents without altering the structural design of the transistors or circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If structural changes are made to reduce leakage current (e.g., dual-gate TFT, reducing channel width, increasing channel length), then leakage current is reduced, but transistor size increases and design flexibility decreases
Solution Approach 1:
The patent applies parameter changes by modifying the electrical characteristics (voltage and time parameters) of the transistor rather than its physical structure. Specifically, it uses a two-stage aging process with different voltage combinations to alter the electrical state of the transistor, reducing leakage current without changing transistor dimensions or structural design, thus maintaining design flexibility while achieving the desired reduction in harmful leakage current
Solution Approach 2:
The patent replaces mechanical/structural modification approaches with an electrical field-based approach. Instead of physically altering the transistor structure (mechanical system), it uses controlled voltage application to create electric fields that modify the transistor's electrical properties and reduce leakage current, thereby avoiding the size increase associated with structural changes
2Object-generated harmful factors
If channel width is reduced to decrease leakage current, then leakage current decreases, but transistor area increases and integration is limited
Solution Approach 1:
The patent changes the electrical parameters (voltage and time) applied to the transistor during aging instead of modifying the physical dimensions. By applying specific voltage combinations in two stages, it reduces leakage current while maintaining the original transistor area, thus resolving the contradiction between reducing harmful leakage and maintaining compact device area for integration
3Object-generated harmful factors
If channel length is increased to reduce leakage current, then leakage current is reduced, but transistor size increases and adaptability to complex pixel circuits decreases
Solution Approach 1:
The patent modifies electrical parameters (voltage and time characteristics) rather than physical dimensions. The two-stage aging process with controlled voltage application reduces leakage current while preserving the original transistor size and structure, thereby maintaining adaptability to complex pixel circuits without the constraints imposed by increased channel length
Solution Approach 2:
The patent applies preliminary electrical stress (aging) to the transistor before it is integrated into the final circuit. This preliminary action of applying controlled voltage stress modifies the transistor's electrical characteristics in advance, reducing leakage current so that the transistor can then be freely integrated into complex pixel circuits without requiring structural modifications
Data Source
Figure 1~2(a)
Figure 2(b)~3
Figure 4~5
AI summary
The present disclosure relates to a method of electrically aging a PMOS thin film transistor. The method includes applying a first voltage Vg with an amplitude of A volts to a gate of the PMOS thin film transistor; applying a second voltage Vs with an amplitude of (A-40) to (A-8) volts to a source of the PMOS thin film transistor; and applying a third voltage Vd with an amplitude of (A-80) to (A-16) volts to a drain of the PMOS thin film transistor. Application of the first voltage Vg, the second voltage Vs and the third voltage Vd is maintained for a predetermined time period, and Vd-Vs < 0. In this way, reduction of a leakage current of the PMOS thin film transistor is achieved without changing a structural design of the thin film transistor.