Balancing pMOS Threshold Voltage via Local Stress Compensation
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Solution Overview
Problem
In integrated circuits, the proximity of pMOS transistors to the border of the active silicon zone leads to relaxation of compressive stress in their channels, causing an increase in threshold voltage and imbalancing of transistor pairs, resulting in performance losses, especially at smaller technological nodes.
Innovation Solution
The solution involves using a pMOS transistor structure with a lower threshold voltage level in regions farther from the active zone border to compensate for stress relaxation, by incorporating transistors with identical structure but different dopant concentrations or work functions, maintaining balanced threshold voltages across the circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If pMOS transistors are positioned near the border of the active silicon zone to increase circuit density, then the circuit integration density is improved, but the compressive stress in the channel is relaxed causing threshold voltage increase and transistor pair imbalance
Solution Approach 1:
The patent applies different transistor structures in different spatial locations within the active zone. Specifically, pMOS transistors positioned near the border (within distance D from the active zone border) use a first structure with higher threshold voltage, while those farther from the border use a second structure with lower threshold voltage. This local differentiation compensates for stress relaxation effects and maintains transistor pair balance across the circuit.
2Ease of manufacture
If the threshold voltage of pMOS transistors near the active zone border is allowed to increase due to stress relaxation, then the manufacturing simplicity is improved, but the cell performance is degraded due to transistor pair imbalance
Solution Approach 1:
The patent implements local quality by distinguishing between two regions: a first region near the active zone border where pMOS transistors use a first structure, and a second region farther from the border where pMOS transistors use a second structure. This spatially-dependent structure selection maintains cell performance without requiring complex global adjustments to the manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively balances the threshold voltages of transistor pairs, reducing performance losses and maintaining efficient operation even at smaller technological nodes by minimizing the impact of stress relaxation on pMOS transistors near the active zone borders.
Implementation Method 1
it is known to form its source and drain of an SiGe alloy, in order to induce a compressive stress in the channel in the direction of transport. Such a stress is typically created by epitaxial growth of SiGe to form the source and the drain.
Implementation Method 2
Such a stress is typically created by epitaxial growth of SiGe to form the source and the drain.
Implementation Method 3
the channel of the nMOS transistor and the channel of the pMOS transistor moreover have concentrations of dopants that are generally identical for one and the same pair. It is known that the addition of dopants into the channel of the transistors makes it possible to modify the threshold voltage of the transistors.
Data Source
AI summary
An integrated circuit is provided, including a first pair including a first nMOS transistor and a first pMOS transistor; a second pair including a second nMOS transistor and a second pMOS transistor; the first and second pMOS transistors including a channel that is subjected to compressive stress and made of an SiGe alloy, and a gate of said transistors being positioned at least 250 nm from a border of an active zone of said transistors; a third pair including a third nMOS transistor having a same construction as the first nMOS transistor and a third pMOS transistor having a same construction as the second pMOS transistor and exhibiting a compressive stress that is lower by at least 250 MPa, the gate of said transistors of the third pair being positioned at most 200 nm from the border.