Wafer Level Reliability Testing for PMOS Threshold Voltage Shifts
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Solution Overview
Problem
Standard wafer level reliability tests fail to detect reliability issues associated with threshold voltage shifts in semiconductor elements, particularly in PMOS elements, which can lead to failures during product level reliability testing, as they do not adequately assess the effects of carrier traps and vertical fields.
Innovation Solution
The method involves forming a gate oxide layer with a thickness of less than 50 Å and a PMOS element with a channel length of less than 0.13 μm, and assessing hot carrier injection (HCl) under specific voltage conditions, including Vg=Vd=Vop, with additional tests such as substrate hot carrier injection (sub-HCl), hot electron induced punch through (HEIP), and channel hot carrier (CHC) tests to detect threshold voltage shifts and ensure wafer level reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard wafer level reliability tests are performed, then manufacturing efficiency is maintained, but reliability detection capability deteriorates due to inability to detect threshold voltage shifts
Solution Approach 1:
The patent applies preliminary action by performing HCl testing on PMOS elements at the wafer level before packaging, to detect potential threshold voltage shift issues early in the manufacturing process. This preliminary detection prevents reliability failures from reaching the product level, resolving the contradiction by enhancing reliability detection capability while maintaining manufacturing efficiency through early intervention.
Solution Approach 2:
The patent applies parameter changes by modifying the testing approach specifically for PMOS elements with thin gate oxide layers and short channel lengths. By adjusting test parameters to account for the unique characteristics of these devices (where hole trapping has significant impact), the patent enhances reliability detection capability without requiring complete redesign of the entire test system, thus managing device complexity.
2Measurement precision
If conventional HCl testing is performed on PMOS elements, then standard reliability assessment is completed, but detection precision deteriorates due to inadequate assessment of carrier trap effects
Solution Approach 1:
The patent applies local quality by implementing enhanced HCl testing specifically for PMOS elements with thin gate oxide layers and short channel lengths, rather than applying uniform testing to all elements. This targeted approach improves measurement precision for threshold voltage shift detection in critical devices while conserving testing resources by focusing efforts where they are most needed.
Solution Approach 2:
The patent applies partial action by performing additional HCl testing on PMOS elements beyond the standard testing protocol. This excessive action in specific cases (PMOS with thin oxide and short channel) improves detection precision for threshold voltage shifts caused by carrier traps, while the partial application to only affected element types manages the consumption of testing resources.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances wafer level reliability by detecting potential offset voltage shift failures and threshold voltage shifts caused by vertical fields, reducing the likelihood of product level reliability issues and improving the detection of semiconductor element deterioration.
Implementation Method 1
assessing hot carrier injection (HCl) under specific voltage conditions, including Vg=Vd=Vop
Implementation Method 2
detecting potential offset voltage shift failures and threshold voltage shifts caused by vertical fields
Data Source
AI summary
A method for ensuring wafer level reliability is provided. The method involves: forming a gate oxide layer having a thickness of less than 50 Å on a semiconductor substrate; forming a PMOS element having a channel length of less than 0.13 μm on the semiconductor substrate; and assessing hot carrier injection (HCl) for the PMOS element.