PMOS-Only Voltage Reference Circuit for Trim-Free Low-Power IoT
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Solution Overview
Problem
Conventional voltage references in low-power systems, such as sensors and IoT devices, face challenges with high power consumption and sensitivity to process variations due to the use of native transistors, which require complex post-fabrication trimming and additional fabrication costs.
Innovation Solution
An ultra-low power PMOS-only voltage reference circuit is designed using two PMOS transistors in a stacked arrangement with a bias circuit, where the threshold voltages of the transistors are matched and the body terminal of the first MOSFET is biased differently, reducing process variations and eliminating the need for trimming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional bandgap voltage references are used, then excellent uniformity across process variation and temperature is achieved, but power consumption increases to μW range
Solution Approach 1:
The patent extracts and eliminates the native transistor component from the voltage reference circuit, using only standard PMOS transistors instead. This extraction removes the source of process variation sensitivity while maintaining the voltage reference function, achieving low power consumption without requiring the complex bandgap structure.
Solution Approach 2:
The patent changes the transistor type parameter from native transistors to standard PMOS transistors, and operates them in the sub-threshold region with specific body biasing. This parameter change enables the circuit to achieve both low power consumption and tolerance to process variations without requiring post-fabrication trimming.
2Use of energy by moving object
If sub-threshold voltage references with native transistors are used, then power consumption is reduced to sub-nW, but sensitivity to process variations increases
Solution Approach 1:
The patent uses only PMOS transistors with the same type of charge carrier throughout the circuit, creating homogeneity in device characteristics. This homogeneous approach eliminates the corner-matching issues between native and standard transistors, reducing sensitivity to process variations while maintaining sub-nW power consumption.
Solution Approach 2:
The patent creates a simplified copy of the voltage reference function using only PMOS transistors in a stacked arrangement, eliminating the need for native transistors. This copying approach with matched threshold voltages achieves process variation tolerance without the complexity and power consumption of conventional solutions.
3Reliability
If post-fabrication trimming is applied, then impact of process variations is alleviated, but area overhead and testing complexity increase
Solution Approach 1:
The voltage reference circuit is designed to be self-tolerant to process variations through its inherent symmetric PMOS structure and body biasing technique. The circuit automatically compensates for process variations without requiring external trimming mechanisms, memory elements, or additional calibration steps, thereby eliminating area overhead and testing complexity.
4Temperature
If native NMOS with stacked PMOS diodes are combined, then reference voltage is increased, but variation across corners is enlarged
Solution Approach 1:
The patent segments the voltage reference function into two separate PMOS transistors with matched threshold voltages in a stacked arrangement. This segmentation allows each transistor to contribute equally to the reference voltage while maintaining consistent performance across process corners, avoiding the variation enlargement that occurs when combining different transistor types.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves a low power consumption of 114 pW and a 0.986V output reference voltage with minimal inaccuracy (1.9% wafer-to-wafer variation) and temperature independence, suitable for low-power applications without the need for post-fabrication trimming.
Implementation Method 1
the body terminal of the first MOSFET is biased with a voltage that is different than the voltage at the source terminal and the voltage at the drain terminal
Implementation Method 2
the threshold voltage of the first MOSFET and threshold voltage of the second MOSFET are designed to be the same and the gate terminal of the second MOSFET is coupled to the drain terminal of the second MOSFET
Data Source
AI summary
A sub-nW voltage reference is presented that provides inherently low process variation and enables trim-free operation for low-dropout regulators and other applications in nW microsystems. Sixty chips from three different wafers in 180 nm CMOS are measured, showing an untrimmed within-wafer σ/μ of 0.26% and wafer-to-wafer σ/μ of 1.9%. Measurement results also show a temperature coefficient of 48-124 ppm/° C. from −40° C. to 85° C. Outputting a 0.986V reference voltage, the reference operates down to 1.2V and consumes 114 pW at 25° C.