PMOS Voltage Regulator Stability for Capacitive Loads
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Solution Overview
Problem
Existing voltage regulator architectures face challenges in providing stability across a wide range of capacitive loads and achieving good current load regulation, particularly due to high dropout voltage and poor load regulation characteristics.
Innovation Solution
A regulator structure comprising a high gain differential amplifier, a low gain differential amplifier, and a replica regulator circuit with a current mirror, where the drain of a second pmos transistor is coupled to the gate of a first pmos transistor to replicate the regulated voltage, and a variable voltage reference generator adjusts the reference voltage based on sensed load current to improve load regulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If an nmos driver is used in the regulator architecture, then the regulator can be stable for both low and high capacitive loads, but the dropout voltage becomes large due to the Vgs requirement
Solution Approach 1:
The patent changes the transistor type parameter from NMOS to PMOS for the driver transistor. PMOS transistors have different electrical characteristics including lower gate-to-source voltage requirements compared to NMOS, which directly reduces the dropout voltage while maintaining the ability to drive both low and high capacitive loads effectively.
2Device complexity
If no feedback is taken directly from Vout, then the regulator architecture is simpler, but the output voltage control becomes poor and load regulation deteriorates
Solution Approach 1:
The patent implements a feedback mechanism by taking a portion of the output voltage through a voltage division network (resistors R1 and R2) and feeding it back to the non-inverting input of the error amplifier. This feedback loop enables precise output voltage control and good load regulation by continuously comparing the divided output voltage with the reference voltage and adjusting the driver transistor accordingly.
3Power
If a high capacity regulator is used in run mode, then the regulator can handle high current demands, but the current consumption increases compared to lower capacity regulators
Solution Approach 1:
The patent employs dynamic mode switching between a high capacity regulator (first regulator) and a lower capacity regulator (second regulator) based on the actual load conditions. During high current demands (run mode), the high capacity regulator is activated. During low current demands (standby or back-up modes), the system switches to the lower capacity regulator, thereby reducing current consumption while maintaining the ability to handle high current when needed.
Data Source
AI summary
A regulator structure includes a first differential amplifier having a first input coupled to a reference voltage node. A second differential amplifier has a first input coupled to the output of the first differential amplifier. A third differential amplifier has a first input coupled to the output of the first differential amplifier. A first pmos transistor has its gate coupled to the second differential amplifier output, and its drain coupled to a second input of each of the first and second differential amplifiers. A second pmos transistor has its gate coupled to the third differential amplifier output, and its drain configured to output a regulated voltage which is also a second input of the third differential amplifier. A circuit is configured to replicate the regulated voltage and couple the replicated regulated voltage to the drain of the first pmos transistor.